Semiconductor Lead Frame Plating Regions for Wire Bonding
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Solution Overview
Problem
The challenge is to increase the number of output leads in semiconductor packages without changing the package size, while reducing costs associated with high Au plating prices and technical difficulties in using wires of different diameters for current flow requirements.
Innovation Solution
A semiconductor device design that uses a combination of thin Au wires and thick Al wires with distinct plating regions for wire bonding, where the Au wire is connected to a first plating region on the periphery and the Al wire to a second plating region on the die pad, allowing for efficient and cost-effective wire bonding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If thick Au plating is used for all wire bonding regions, then reliable wire bonding for both thin and thick wires is achieved, but manufacturing cost increases due to high Au plating prices
Solution Approach 1:
The patent applies different plating materials to different regions of the lead terminal based on local requirements. The first region (peripheral region) receives Au plating for reliable bonding with thin Au wires, while the second region (central region) receives Al plating for cost-effective bonding with thick Al wires. This local differentiation resolves the contradiction by providing high reliability only where necessary (thin wire bonding) while reducing costs in other areas (thick wire bonding).
Solution Approach 2:
The lead terminal surface is divided into two distinct regions: a first region and a second region, each with different plating compositions. This segmentation allows the patent to apply Au plating only to the first region where thin wire bonding is performed, while applying Al plating to the second region for thick wire bonding, thereby reducing overall Au plating usage and manufacturing costs while maintaining bonding reliability where needed.
2Ease of manufacture
If single wire diameter is used for all connections, then manufacturing process is simplified, but current flow requirements for power device outputs cannot be optimized
Solution Approach 1:
The patent assigns different wire diameters to different functional regions: thin wires (e.g., Au wires) are used for control signal connections where low current flow is sufficient, while thick wires (e.g., Al wires) are used for power output connections requiring high current flow capability. This local optimization of wire diameter resolves the contradiction by simplifying the manufacturing process through standardized bonding techniques while enhancing current flow capability where required for power device outputs.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the cost of semiconductor devices by avoiding the use of single, thick Au plating and ensures reliable wire bonding for both thin and thick wires, enabling increased output leads without size increases, thus enhancing functionality.
Implementation Method 1
a first plated surface composed of a metal containing nickel as a main component is formed in a half region on a lead-out-part side of a pad part of each lead terminal, and in which a second plated surface made of a metal containing silver as a main component is formed in a half region close to an edge part of a supporting plate of the pad part
Data Source
AI summary
A method of manufacturing a semiconductor device includes preparing a lead frame provided with a die pad having an upper surface and a plurality of leads being arranged so as to be aligned on a side of the die pad and each including a wire joint part at a distal end on the side of the die pad, after the preparing the lead frame, mounting a semiconductor chip having a main surface and a plurality of electrode pads formed on the main surface, on the upper surface of the die pad, and after the mounting the semiconductor chip, electrically connecting a first electrode pad among the plurality of electrode pads of the semiconductor chip and a first lead among the plurality of leads to each other via a first wire.