Semiconductor Plug Alignment via Zigzag Patterning and Protection Masks
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Solution Overview
Problem
As semiconductor devices integrate more layers, the reduced space between patterns and interconnections increases the risk of misalignment, leading to potential malfunctions and decreased device reliability due to incorrect connections.
Innovation Solution
A method involving the formation of plugs in a zigzag pattern within an interlayer insulating layer, with a protection pattern and molding patterns that allow for precise alignment and electrical connection of interconnections, using materials like silicon nitride and silicon oxide, and a double patterning technique to ensure accurate placement and etching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If interconnections are disposed in multiple layers with reduced space between patterns, then integration density is improved, but alignment precision deteriorates
Solution Approach 1:
The patent divides the alignment process into multiple stages using different mask patterns (first alignment mark, second alignment mark, third alignment mark) positioned at different locations. Each mask pattern serves a specific alignment function for different interconnection layers, enabling precise alignment even with reduced spacing between patterns.
Solution Approach 2:
The patent introduces alignment marks as intermediary elements that facilitate the alignment process. These marks serve as reference points between different interconnection layers, allowing the formation apparatus to accurately position plugs and interconnections even when the space between patterns is reduced.
2Quantity of substance
If alignment margin is reduced due to reduced space between patterns, then integration density is improved, but reliability deteriorates
Solution Approach 1:
The patent performs preliminary alignment by forming alignment marks and using them as references before forming the actual interconnections. The first alignment mark is formed before plugs, the second alignment mark is formed between plugs, and the third alignment mark is formed after plugs. This preliminary alignment action ensures that even with reduced alignment margin, the final interconnections are accurately positioned, maintaining device reliability.
Solution Approach 2:
The patent implements a feedback mechanism where alignment marks are formed and used to guide subsequent formation steps. The alignment marks provide real-time reference information that allows the formation apparatus to adjust and maintain precise positioning, ensuring reliable connections despite reduced space between patterns.
3Quantity of substance
If plugs are formed with smaller intervals, then integration density is improved, but manufacturing precision deteriorates
Solution Approach 1:
The patent uses asymmetric positioning of alignment marks relative to plugs. The first alignment mark is positioned at a first interval from plugs, the second alignment mark is positioned at a second interval between plugs, and the third alignment mark is positioned at a third interval after plugs. These different intervals create an asymmetric alignment system that provides multiple reference points, enabling precise plug placement even when plugs are formed with smaller intervals for higher integration density.
Data Source
AI summary
A semiconductor device may include plugs disposed in a zigzag pattern, interconnections electrically connected to the plugs and a protection pattern which is interposed between the plugs and the interconnections to selectively expose the plugs. The interconnections may include a connection portion which is in contact with plugs selectively exposed by the protection pattern. A method of manufacturing a semiconductor device includes, after forming a molding pattern and a mask pattern, selectively etching a protection layer using the mask pattern to form a protection pattern exposing a plug.