Semiconductor Plug Formation via Segmented Through Holes
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Solution Overview
Problem
Conventional photolithography processes struggle to form small pitch plugs in semiconductor devices due to physical limits, leading to short circuits and poor performance, as they require multiple patterned layers and increased manufacturing costs.
Innovation Solution
A method involving the formation of through holes in an interlayer dielectric layer to expose doped source/drain regions, with subsequent plugs formed in these holes, allowing for reduced pitch without increasing the number of patterned layers or process steps, thereby preventing short circuits and enhancing device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional one-step photolithography process is used, then the process is simple, but short circuits are easily formed between adjacent plugs due to inability to form small pitch plugs
Solution Approach 1:
The patent segments the plug formation process into multiple stages: first forming a mandrel structure, then forming a first patterned layer with first openings, followed by forming a second patterned layer with second openings that overlap with first openings. This segmentation allows precise control of plug positions and prevents short circuits while achieving small pitch plugs that conventional one-step photolithography cannot form.
2Manufacturing precision
If multiple patterned layers are used to form small pitch plugs, then manufacturing precision improves, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent merges the formation of multiple plugs into a single integrated process by forming first and second patterned layers with overlapping openings in one continuous operation. The mandrel structure serves as a common reference for both patterned layers, allowing precise alignment and formation of small pitch plugs without requiring separate photolithography processes, thereby reducing device complexity while maintaining high manufacturing precision.
Data Source
AI summary
Semiconductor device and formation method are provided. The method includes providing a substrate, a first fin and a second fin on the substrate, an isolation structure covering a portion of sidewalls of the first and second fins, a gate structure across the first fin or the second fin, a first doped source/drain region in the first fin, a second doped source/drain region in the second fin, and an interlayer dielectric layer on the isolation structure, the first and second fins, and the gate structure. A first through hole is formed in the interlayer dielectric layer, exposing the first doped source/drain region or the second doped source/drain region. A second through hole is formed in the interlayer dielectric layer on the isolation structure to connect to the first through hole. A first plug is formed in the first through hole and a second plug is formed in the second through hole.