Semiconductor Plug Structure for Selective Metal Growth Morphology

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Solution Overview

Problem

The performance of semiconductor structures, particularly in terms of conductivity and integration density, is limited by the conventional selective metal growth process used for forming connection plugs, which results in poor morphology and increased risk of open circuits due to premature closure of openings and cavity formation.

Innovation Solution

A method involving the formation of a first plug in a dielectric layer, followed by a second dielectric layer covering the first plug, and subsequent selective metal growth of a second plug material film, which reduces material deposition on the first plug and enhances adhesion and conductivity by using gases like WF6 and H2 at specific temperature and flow rate ranges.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional selective metal growth process is used to form connection plugs, then low resistivity and good conductivity are achieved, but poor morphology and high risk of open circuits occur due to premature closure of openings and cavity formation

Engineering Contradiction:
ImproveconductivityVSAvoidmorphology
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

A first plug is formed in the first dielectric layer before forming the second plug. This preliminary structure provides a foundation that prevents premature closure of openings during subsequent metal growth, eliminating cavity formation while maintaining the low resistivity benefits of selective metal growth.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The connection plug formation is divided into two separate plugs formed at different stages. The first plug is formed in the first dielectric layer, and the second plug is formed subsequently with improved morphology control. This segmentation allows each plug to be optimized independently, resolving the contradiction between conductivity and morphology.

Inventive Principle:
Principle #1Segmentation

2Area of stationary object

If connection plug is formed on gate structure over isolation region, then area is saved for higher integration degree, but manufacturing complexity increases

Engineering Contradiction:
Improvewafer surface areaVSAvoidfabrication process complexity
Core Design Contradiction:
Area of stationary objectVSDevice complexity

Solution Approach 1:

The first dielectric layer serves multiple functions: it acts as an insulating layer, provides a structural foundation for the first plug, and enables subsequent plug formation. This multi-functionality reduces the need for additional separate structures, simplifying the overall fabrication process while maintaining high integration density.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach improves the morphology and conductivity of the semiconductor structure by protecting the first plug from subsequent processes and allowing direct deposition of the second plug material, reducing the influence on the second plug film and enhancing its performance.

Implementation Method 1

forming a second plug material film in the first dielectric layer and the second dielectric layer. The second plug material film is in contact with one of the top surface of the source-drain plug and the top surface of the gate structure

Methodology Applied
Scientific EffectSelective metal growth:

Implementation Method 2

forming the second plug material film includes a selective metal growth process, a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process

Methodology Applied
Scientific EffectChemical vapor deposition: Chemical Vapour Deposition

Data Source

PatentUS11908906B2Semiconductor structure and fabrication method thereof
Publication Date: 2024.02.20 SEMICON MFG INT (SHANGHAI) CORP
  • US11908906B2 patent drawing
  • US11908906B2 patent drawing
  • US11908906B2 patent drawing

AI summary

A semiconductor structure and a fabrication method of the semiconductor structure are provided. The method includes providing a substrate, forming a first dielectric layer and a plurality of gate structures, forming source-drain doped regions, and forming a source-drain plug. The first dielectric layer covers surfaces of the gate structure, the source-drain doped region and the source-drain plug. The method also includes forming a first plug in the first dielectric layer, and forming a second dielectric layer on the first dielectric layer. The first plug is in contact with a top surface of one of the source-drain plug and the gate structure. The second dielectric layer covers the first plug. Further, the method includes forming a second plug material film in the first and second dielectric layers. The second plug material film is in contact with the top surface of one of the source-drain plug and the gate structure.