Semiconductor Plug Layout Noise Prevention
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Solution Overview
Problem
In highly miniaturized semiconductor integrated circuit cells, it is challenging to maintain sufficient spacing between power-feeding plugs and signaling plugs to prevent noise-induced malfunctions while achieving further chip miniaturization without degrading circuit reliability.
Innovation Solution
A method involving the deletion of power-feeding plugs that cannot be sufficiently spaced from signaling plugs in the layout design, ensuring that power-feeding plugs are not placed within a specific distance from signaling plugs to prevent operational impairment, thereby allowing for miniaturization without expanding the circuit cell size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If power-feeding plugs are placed densely to achieve miniaturization, then chip area is reduced, but noise-induced malfunctions occur due to insufficient spacing from signaling plugs
Solution Approach 1:
The patent extracts and removes power-feeding plugs from positions that are too close to signaling plugs. The layout design process identifies and deletes power-feeding plugs within a predetermined distance from signaling plugs, thereby eliminating the source of noise interference while maintaining miniaturization in other areas of the chip.
Solution Approach 2:
The patent applies local quality by creating spatially varying plug density across the chip. In regions near signaling plugs, power-feeding plugs are sparse or absent to prevent noise interference, while in other regions, plugs are placed densely to achieve miniaturization. This localized adjustment of plug distribution optimizes both reliability and area utilization.
2Reliability
If spacing between power-feeding plugs and signaling plugs is increased to prevent noise interference, then circuit reliability is improved, but chip area increases
Solution Approach 1:
Rather than uniformly increasing spacing across the entire chip, the patent selectively removes only those power-feeding plugs that are too close to signaling plugs. This targeted extraction approach maintains reliability by eliminating noise sources while avoiding unnecessary area expansion in regions where dense packing is acceptable.
Solution Approach 2:
The patent applies partial action by implementing spacing constraints only in specific critical regions near signaling plugs, rather than applying uniform spacing rules across the entire chip. This allows maximum area utilization in non-critical regions while ensuring reliability in critical regions.
3Area of moving object
If circuit cell size is reduced for miniaturization, then chip area is reduced, but it becomes difficult to maintain sufficient plug spacing
Solution Approach 1:
The patent applies preliminary action by establishing spacing constraints and deleting inappropriate power-feeding plugs during the layout design phase, before manufacturing. This preliminary adjustment of plug positions ensures that spacing requirements are met from the design stage, simplifying the manufacturing process and avoiding costly post-manufacturing adjustments.
Solution Approach 2:
The patent uses automated layout design tools that copy and paste standardized cell structures while automatically adjusting plug positions to meet spacing constraints. This copying approach with automated adjustment maintains design consistency across multiple cells while adapting to miniaturization requirements.
Data Source
AI summary
To provide a circuit layout design method that can prevent degradation of the circuit reliability even in highly miniaturized circuit cells.In order to prevent noise from a power supply potential or a reference potential with a large potential difference from affecting a gate electrode and causing a malfunction, a first plug connected to the gate electrode and a second plug to which the power supply potential or the reference potential is supplied are required to be spaced from each other by a distance sufficient for the noise from the power supply potential or the reference potential not to affect the first plug. To this end, among the second plugs placed at equal intervals under the wiring, only the second plug placed at a layout position that is not sufficiently spaced from the first plug is deleted at the time of planar layout design.