Semiconductor Plug Planarization via Self-Orientation Spacer
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Solution Overview
Problem
The challenge in manufacturing ferroelectric memory devices is the difficulty in achieving a sufficiently planarized surface for the plug conductive layer, which affects the crystal orientation and ferroelectric properties of the capacitor, due to the use of tungsten, which has large crystal grains and uneven surfaces, leading to recesses and defective filling during polishing.
Innovation Solution
A semiconductor device is developed with a spacer dielectric film and a spacer conductive section having self-orientation characteristics, embedded in a hole section of the spacer dielectric film, which allows for uniform and deeper thickness, preventing removal during polishing and ensuring well-aligned crystal orientation, and a hydrogen barrier property to prevent degradation of the ferroelectric capacitor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If tungsten is used as the plug conductive layer material, then electrical conductivity is improved, but surface planarity deteriorates due to large crystal grains and uneven surfaces
Solution Approach 1:
A planarization layer is introduced as an intermediary component between the tungsten plug conductive layer and the overlying interlayer dielectric film. This planarization layer serves as a mediator that compensates for the surface unevenness of the tungsten layer, providing a flat surface for subsequent processing while preserving the electrical conductivity benefits of the tungsten plug.
2Manufacturing precision
If the tungsten plug conductive layer surface is planarized by polishing, then surface flatness is improved, but recesses are generated in the surface
Solution Approach 1:
The planarization layer is applied beforehand to compensate for surface unevenness before subsequent polishing operations. This layer acts as a cushion that prevents the formation of deep recesses during polishing, maintaining surface uniformity while achieving the necessary flatness for overlying structures.
3Manufacturing precision
If the surface is planarized by polishing after recesses are filled with conductive body, then surface flatness is improved, but portions of the conductive body at shallow recesses are removed and uneven surface is partially exposed
Solution Approach 1:
The planarization layer is applied preliminarily before filling recesses with conductive body. This preliminary action creates a uniform base that prevents the need for subsequent polishing that would remove filled material and expose uneven surfaces, thereby maintaining both flatness and uniformity.
4Ease of manufacture
If ferroelectric capacitor is formed on uneven tungsten surface, then manufacturing process is simplified, but crystal orientation is deviated and ferroelectric property is deteriorated
Solution Approach 1:
The planarization layer serves as an intermediary between the uneven tungsten surface and the ferroelectric capacitor formation process. This layer provides a flat surface that enables proper crystal orientation of the ferroelectric capacitor without complicating the overall manufacturing process, thus resolving the contradiction between ease of manufacture and manufacturing precision.
5Reliability
If plug conductive layer is formed on ferroelectric capacitor, then electrical connection is improved, but defective filling occurs due to unevenness of tungsten surface
Solution Approach 1:
The planarization layer acts as an intermediary that provides a uniform surface for forming the plug conductive layer on the ferroelectric capacitor. This eliminates defective filling caused by underlying tungsten surface unevenness, ensuring complete and uniform filling while maintaining good electrical connection.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively planarizes the plug conductive layer, maintains well-aligned crystal orientation, and prevents hydrogen penetration, resulting in improved ferroelectric characteristics and reduced defects in the ferroelectric capacitors.
Implementation Method 1
a spacer conductive section embedded in a hole section of the spacer dielectric film, connected to the plug conductive layer and connected to the conducive member, wherein the spacer conductive section is formed from a conductive material having a self-orientation characteristic
Implementation Method 2
a hydrogen barrier property to prevent degradation of the ferroelectric capacitor
Data Source
AI summary
A semiconductor device is equipped with a plug conductive layer formed in an interlayer dielectric film on a substrate, and a conductive member provided on the plug conductive layer. The semiconductor device further includes a spacer dielectric film formed on the interlayer dielectric film and having a hole section connecting to the plug conductive layer; and a spacer conductive section embedded in the hole section of the spacer dielectric film, connected to the plug conductive layer and connected to the conducive member, wherein the spacer conductive section is formed from a conductive material having self-orientation characteristic, and a top surface of the spacer dielectric film and a top surface of the spacer conductive section are planarized.