Point-Symmetric Chip Pads for Semiconductor Package Substrate Space Reduction
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Solution Overview
Problem
Current semiconductor package technologies face challenges in optimizing the arrangement of power and ground pads on semiconductor chips for efficient electrical connections and reduced package size, leading to increased complexity and space requirements for bond finger arrays.
Innovation Solution
The semiconductor package design features semiconductor chips with point-symmetrically arranged power and ground pads on both sides of the chip body, allowing for overlapping connections with bond finger arrays on the package substrate, which reduces the number of power and ground fingers needed, thereby minimizing space and enhancing design flexibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If power and ground pads are arranged on both sides of the chip body with point symmetry, then the number of bond fingers required is reduced, but the pad arrangement complexity increases
Solution Approach 1:
The patent applies point symmetry (a form of asymmetric arrangement) to the pad layout, where pads on opposite sides of the chip body are positioned symmetrically with respect to a reference point. This asymmetric yet balanced arrangement allows bond fingers to serve multiple chips simultaneously, reducing the total number of bond fingers required while maintaining systematic organization that manages complexity.
Solution Approach 2:
The pad arrangement enables bond fingers to perform multiple functions by serving adjacent chips in a stacked configuration. The point-symmetric layout allows a single bond finger to connect to corresponding pads on multiple chips, making the bond finger structure multi-functional and reducing the overall quantity needed.
2Area of stationary object
If pads are arranged to overlap between stacked chips, then space on package substrate is reduced, but electrical connection complexity increases
Solution Approach 1:
The patent transitions from a two-dimensional pad arrangement to a three-dimensional stacked configuration with point symmetry. By arranging pads on multiple levels (stacked chips) with overlapping projections, the design utilizes the vertical dimension to reduce the horizontal footprint on the package substrate while maintaining systematic electrical connections through the stack.
Solution Approach 2:
The overlapping pad arrangement between stacked chips creates a nested structure where pads on upper chips are positioned to overlap with pads on lower chips. This nesting allows multiple connection points to occupy the same projected area, reducing the overall space required on the package substrate while organizing electrical connections in a hierarchical manner.
Data Source
AI summary
A semiconductor package according to an aspect of the present disclosure includes a package substrate and a plurality of semiconductor chips stacked on the package substrate. Each of the semiconductor chips includes a chip body, at least one first side power pad and at least one first side ground pad that are disposed on a first side portion on one surface of the chip body, and at least one second side power pad and at least one second side ground pad that are disposed on a second side portion opposite to the first side portion on one surface of the chip body. One of the second side power pads is disposed point-symmetrically to corresponding one of the first side power pads with respect to a reference point on the one surface, and one of the second side ground pads is disposed point-symmetrically to corresponding one of the first side ground pads with respect to a reference point on the one surface.