Semiconductor Packaging Layout With In-Situ Polymer and Thin Vias
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Solution Overview
Problem
Current semiconductor device manufacturing processes face challenges in reducing size and material usage while maintaining efficiency and connectivity, particularly in forming compact and efficient semiconductor devices with complex structural and functional requirements.
Innovation Solution
The process involves forming a semiconductor device with a substrate, active devices, interlayer dielectric layers, metallization layers, a top metal layer, a first passivation layer, a first redistribution layer, a polymer protective layer, and conductive vias, where the polymer protective layer is formed in situ to eliminate the need for additional passivation and reduce material usage, and the conductive vias are formed with a thickness less than 15 μm to minimize pitch and material consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If conventional manufacturing processes are used with multiple passivation layers and thicker conductive vias, then device reliability and connectivity are maintained, but device size and material usage increase
Solution Approach 1:
The patent removes the intermediate first passivation layer between the interlayer dielectric and the polymer protective layer, extracting unnecessary components to reduce device size and material usage while maintaining the essential protective and insulating functions through the remaining structure
Solution Approach 2:
The patent reduces the conductive via thickness to less than 15 μm from conventional thicker dimensions, changing the via thickness parameter to minimize pitch and material consumption while maintaining electrical connectivity through optimized via design
2Object-affected harmful factors
If additional passivation layers are used, then device protection and insulation are improved, but material usage and manufacturing complexity increase
Solution Approach 1:
The patent combines the protective and insulating functions into a simplified structure where the polymer protective layer directly contacts the interlayer dielectric, merging multiple functions into fewer layers and eliminating the need for the first passivation layer
Solution Approach 2:
The polymer protective layer serves multiple functions simultaneously: it provides mechanical protection, electrical insulation, and structural support, making it a multi-functional element that replaces what would traditionally require separate dedicated layers
3Reliability
If thicker conductive vias are formed, then electrical connectivity is ensured, but pitch and material consumption increase
Solution Approach 1:
The patent optimizes the conductive via thickness parameter to less than 15 μm, changing this critical dimension to achieve the right balance between electrical connectivity and material consumption, enabling smaller pitch while maintaining via reliability
Data Source
AI summary
A semiconductor device has a top metal layer, a first passivation layer over the top metal layer, a first redistribution layer over the first passivation layer, a first polymer layer, and a first conductive via extending through the first polymer layer. The first polymer layer is in physical contact with the first passivation layer.