Semiconductor Packaging Polymer Layer for Warpage Reduction
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Solution Overview
Problem
Stacked semiconductor devices experience warpage due to differences in the coefficient of thermal expansion (CTE) of various materials, leading to potential device failure and reduced manufacturing yield, as existing solutions fail to adequately compensate for thermal stress.
Innovation Solution
A semiconductor device design that includes a polymer layer selectively formed on the substrate between external connectors, with varying thicknesses to counteract the thermal expansion mismatch between underfill and molding materials, reducing warpage and preventing cold joints and solder bridges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If stacked semiconductor devices are fabricated with multiple materials, then integration density and functionality are improved, but warpage occurs due to CTE mismatch between materials
Solution Approach 1:
The patent applies parameter changes by modifying the CTE of the substrate through controlled oxidation of the silicon surface. By adjusting oxidation parameters (temperature, time, atmosphere), the substrate's CTE can be tuned to match that of the underfill material, thereby compensating for thermal expansion mismatches and reducing warpage in the stacked semiconductor device.
Solution Approach 2:
The patent employs composite material strategies by creating a multi-layer structure where the oxidized silicon substrate serves as a CTE-matched intermediate layer between the underfill and the semiconductor die. This composite approach allows each layer to contribute its specific properties, with the oxidized substrate acting as a buffer that harmonizes thermal expansion differences among materials.
2Ease of manufacture
If conventional packaging techniques are used, then manufacturing process is simple, but severe warpage causes device failure and reduced yield
Solution Approach 1:
The patent implements preliminary action by performing surface oxidation on the silicon substrate before assembling the stacked semiconductor device. This pre-treatment modifies the substrate's CTE in advance, ensuring that thermal expansion mismatches are compensated before the underfill and die are attached, thereby preventing warpage issues during subsequent manufacturing steps.
Solution Approach 2:
The oxidation process parameters (temperature, duration, oxygen pressure) are optimized to achieve the desired CTE modification of the substrate. By controlling these parameters, the substrate's thermal properties are adjusted to match the underfill material, reducing warpage without adding significant complexity to the manufacturing process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The polymer layer effectively reduces warpage, enhancing the reliability and yield of semiconductor devices by matching the CTE and stress levels of the underfill and molding materials, thereby minimizing thermal-induced stress and electrical shorts.
Implementation Method 1
Due to the differences in the coefficient of thermal expansion (CTE) of different materials used in the stacked semiconductor device, warpage of the stacked semiconductor device may occur
Data Source
AI summary
A semiconductor device includes a substrate, a first redistribution layer (RDL) over a first side of the substrate, one or more semiconductor dies over and electrically coupled to the first RDL, and an encapsulant over the first RDL and around the one or more semiconductor dies. The semiconductor device also includes connectors attached to a second side of the substrate opposing the first side, the connectors being electrically coupled to the first RDL. The semiconductor device further includes a polymer layer on the second side of the substrate, the connectors protruding from the polymer layer above a first surface of the polymer layer distal the substrate. A first portion of the polymer layer contacting the connectors has a first thickness, and a second portion of the polymer layer between adjacent connectors has a second thickness smaller than the first thickness.