Semiconductor Power Cell Layout for Adjustable Rail Resistance

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Solution Overview

Problem

Modifying the timing of transistors in semiconductor devices is difficult due to challenges in changing transistor channel length without significant impacts on resistance, and individual power delivery pillars between circuit elements lead to higher resistance and elevated failure risks.

Innovation Solution

Grouping power delivery pillars into power cells connected in parallel to topside and/or bottom-side power delivery rails, allowing for adjustable resistance and easier circuit matching by adjusting the number of power pillars connected to voltage sources or ground.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If individual power delivery pillars are used between circuit elements, then device complexity is reduced, but resistance increases and reliability deteriorates

Engineering Contradiction:
Improvepower delivery structure complexityVSAvoiddevice failure risk
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent combines multiple individual power delivery pillars into grouped power delivery structures (power cells) that are connected in parallel. This merging approach reduces the overall resistance between circuit elements while distributing the current load across multiple parallel paths, thereby improving reliability without significantly increasing device complexity.

Inventive Principle:
Principle #5Merging (Combining)

2Measurement precision

If transistor channel length is modified to adjust timing, then timing precision is improved, but resistance changes significantly

Engineering Contradiction:
Improvetiming precisionVSAvoidresistance stability
Core Design Contradiction:
Measurement precisionVSReliability

Solution Approach 1:

The patent segments the power delivery function from the transistor timing function. Instead of modifying the transistor channel length to adjust timing, the invention uses separately controllable power delivery structures (power cells with adjustable number of parallel pillars) to independently control timing without affecting transistor resistance characteristics.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent changes the resistance parameter of the power delivery structure by adjusting the number of parallel power pillars in each power cell, rather than changing transistor dimensions. This allows independent control of power delivery resistance without impacting transistor timing characteristics.

Inventive Principle:
Principle #35Parameter changes

3Ease of operation

If transistor dimensions are changed to modify timing, then timing adjustment is achieved, but manufacturing precision requirements increase

Engineering Contradiction:
Improvetiming adjustabilityVSAvoidtransistor dimension control
Core Design Contradiction:
Ease of operationVSManufacturing precision

Solution Approach 1:

The patent introduces dynamic adjustability to the power delivery structure by allowing the number of active power pillars in each power cell to be varied. This dynamic configuration enables timing adjustment through simple switching of parallel connections rather than requiring precise control of transistor dimensions during manufacturing.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS20250324764A1Power cell for semiconductor devices
Publication Date: 2025.10.16 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250324764A1 patent drawing
  • US20250324764A1 patent drawing
  • US20250324764A1 patent drawing

AI summary

A device includes an electrical circuit. The device further includes a first conductive rail electrically connected to the electrical circuit, wherein the first conductive rail is on a first side of a substrate. The device further includes a power pillar electrically connected to the first conductive rail, the power pillar comprises a plurality of vias extending through the substrate, and adjacent vias of the plurality of vias are offset from one another in a direction parallel to a surface of the first side of the substrate.