Semiconductor Power Cell Layout for Low-Resistance Timing Matching
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Solution Overview
Problem
Modifying the timing of transistors in semiconductor devices is difficult due to the challenge of changing transistor channel length without significant impacts on resistance, and individual power delivery pillars between circuit elements lead to higher resistance and elevated failure risks.
Innovation Solution
Arranging power delivery pillars into groups or power cells, connected in parallel to topside and/or bottom-side power delivery rails, allows for adjustable resistance and easier circuit matching by adjusting the number of power pillars to connect to voltage sources or ground, with post-manufacturing adjustments using fuses to regulate resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If individual power delivery pillars are used between circuit elements, then device complexity is reduced, but resistance increases and reliability deteriorates
Solution Approach 1:
Multiple individual power delivery pillars are merged into a grouped power cell structure where multiple pillars work together in parallel. This combining approach reduces overall resistance while distributing the power delivery function across multiple supporting elements, thereby improving reliability without excessive complexity increase.
Solution Approach 2:
The power delivery system is segmented into modular power cells, each containing multiple pillars that can be independently configured. This segmentation allows flexible adjustment of resistance characteristics by varying the number and arrangement of pillars within each cell, optimizing both reliability and complexity management.
2Measurement precision
If transistor channel length is modified to adjust timing, then timing precision is improved, but resistance changes significantly
Solution Approach 1:
Instead of modifying the transistor channel length globally, the invention applies local adjustments through power cell configuration. By varying the number and arrangement of power pillars in specific locations, timing characteristics are adjusted without altering the fundamental transistor geometry, thus maintaining resistance stability while achieving timing precision.
Solution Approach 2:
The invention changes parameters of the power delivery system (number of pillars, their arrangement, connection configurations) rather than changing transistor physical dimensions. This parameter adjustment approach allows timing optimization while keeping transistor channel length and associated resistance characteristics constant.
3Reliability
If power pillars are arranged in groups to decrease resistance, then reliability is improved, but device complexity increases
Solution Approach 1:
The power cell structure serves multiple functions simultaneously: it provides power delivery, adjusts resistance characteristics, enables timing control, and offers configurable connectivity. This multi-functionality reduces the need for separate structures for each function, managing overall device complexity while achieving improved reliability through grouped pillar arrangements.
4Manufacturing precision
If the number of power pillars is increased to adjust resistance, then circuit matching is improved, but manufacturing complexity increases
Solution Approach 1:
The power cell design incorporates adjustable and reconfigurable elements that allow resistance tuning after basic manufacturing. This dynamic configuration capability enables precise circuit matching through selective activation or connection of power pillars, reducing the need for complex manufacturing variations while achieving manufacturing precision.
Data Source
AI summary
A device includes an electrical circuit. The device further includes a first conductive pillar over a first side of a substrate. The device further includes a first conductive rail electrically connected to the first conductive pillar, wherein the electrical circuit is electrically connected to the first conductive rail by the first conductive pillar. The device further includes a power pillar extending through the substrate, wherein the power pillar is electrically connected to the first conductive rail.


