Semiconductor Power Control Circuit Standby State Management
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Solution Overview
Problem
Conventional power management methods in semiconductor devices face challenges in balancing power saving with return time periods from deep standby states, leading to potential system collapses due to long return times and inadequate depth of standby states when task execution changes.
Innovation Solution
A semiconductor device with a CPU, interrupt control circuit, and power control circuit that dynamically adjusts standby state levels based on allowable return time periods for tasks, transitioning to a shallower state if the return time exceeds the allowed period to ensure timely task execution and prevent system collapse.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If a deeper standby state is set to maximize power saving, then power consumption is reduced, but the return time period from standby to operating state becomes longer
Solution Approach 1:
The patent applies dynamics by making the standby state selection changeable based on task characteristics. The power control circuit dynamically adjusts which standby state (first or second) to transition to, depending on the allowable return time period and depth requirements of the currently executed task. This resolves the contradiction by allowing the system to adapt between power saving and response time based on real-time task requirements
Solution Approach 2:
The patent changes the parameter of standby state selection (which specific standby state to transition to) based on task parameters. By evaluating task-specific allowable return time periods and depths, the system selects between multiple standby states with different power consumption and return time characteristics, thus resolving the trade-off between power saving and response time
2Reliability
If a standby state with short return time period is set to ensure system stability, then system collapse is prevented, but power saving opportunity is lost
Solution Approach 1:
The system dynamically determines standby state selection based on task characteristics. When tasks with stringent return time requirements are executed, the first standby state (shorter return time) is selected to ensure reliability. When tasks allow longer return times, the second standby state (deeper, more power-saving) is selected. This dynamic adaptation resolves the contradiction between reliability and power saving
3Loss of energy
If the standby state depth is increased for power saving, then power consumption decreases, but the system may collapse when tasks require faster response
Solution Approach 1:
The patent changes the standby state parameter based on task parameters. Each task has specific allowable return time period and depth requirements. The power control circuit evaluates these task parameters and selects the appropriate standby state accordingly. This parameter-based selection ensures both power saving and task compatibility, resolving the contradiction
Data Source
AI summary
According to an embodiment, a semiconductor device can be in an operating state and a standby state with a choice of a plurality of standby state levels and has a CPU, an interrupt control circuit, and a hardware control circuit. The CPU makes a comparison of a first return time period corresponding to a first standby state level that is a shallowest one selected from among allowable standby state levels set for one or more tasks executed immediately before transition to the standby state with a second return time period selected from among allowable return time periods set for the one or more tasks executed, changes a standby state level of the standby state if the first return time period is judged to be longer than the second return time period as a result of the comparison, and controls the hardware control circuit.