Semiconductor Power Device Multiple Drain Manufacturing Process
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Solution Overview
Problem
Existing multi-drain power electronic devices face challenges in achieving low output resistance and reduced dimensions while maintaining high breakdown voltage, due to limitations in epitaxial layer design and manufacturing processes, which increase costs and affect electrical performance.
Innovation Solution
A process involving selective N dopant implantation and epitaxial growth to form P column regions with reduced lateral size, balanced concentration profiles, and high thermal budget diffusion to achieve low output resistance and scaled dimensions, with the epitaxial layers forming a common drain layer for multiple elementary units.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If the epitaxial layer concentration is increased to reduce output resistance, then the output resistance decreases, but the breakdown voltage also decreases
Solution Approach 1:
The patent applies local quality by creating column regions with high dopant concentration specifically in areas where low resistance is needed, while maintaining lower concentration in other epitaxial layer regions to preserve breakdown voltage. This localized doping strategy allows different parts of the epitaxial layer to have different electrical properties optimized for their specific functions.
Solution Approach 2:
The patent creates a composite structure within the epitaxial layer by forming column regions with different dopant concentration than the surrounding epitaxial material. This composite approach combines regions of high conductivity (column regions) with regions of high breakdown capability (epitaxial layer), achieving both low output resistance and high breakdown voltage simultaneously.
2Productivity
If the pitch of power MOS devices is reduced to increase integration density, then the integration density increases, but the manufacturing precision requirements increase
Solution Approach 1:
The patent uses preliminary action by forming the column regions through epitaxial growth with predetermined dopant concentrations before subsequent processing steps. This pre-establishes the electrical characteristics and geometric boundaries of active regions, making the overall manufacturing process more robust to variations in later steps and enabling tighter pitch control.
3Reliability
If the thickness of epitaxial layers is increased to improve electrical performance, then the electrical performance improves, but the manufacturing cost increases
Solution Approach 1:
The patent applies local quality by varying the dopant concentration within the epitaxial layer to create column regions with high carrier concentration for low resistance, while maintaining lower concentration in other areas. This allows achieving good electrical performance without uniformly increasing epitaxial layer thickness or dopant concentration throughout, thereby controlling manufacturing costs.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The process results in power devices with reduced output resistance, increased thickness of epitaxial layers, and lower pitch, maintaining high breakdown voltage and electrical performance, while reducing manufacturing costs and lateral extension of column regions.
Implementation Method 1
selective N dopant implantation
Implementation Method 2
high thermal budget diffusion to achieve low output resistance
Implementation Method 3
epitaxial growth to form P column regions with reduced lateral size
Data Source
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AI summary
Process for manufacturing a power electronic device (30) comprising the following steps: forming a first semiconductor layer (21) of the first type of conductivity forming at least a second semiconductor layer (22) of a second type of conductivity value on the first semiconductor layer (21), forming, in this at least a second semiconductor layer (22), a first plurality of implanted regions (D1) of the first type of conductivity forming, above said at least a second semiconductor layer (22), a superficial semiconductor layer (26) of the first type of conductivity, forming in the surface semiconductor layer (26) body regions (40) of the second type of conductivity, the body regions (40) being aligned with portions of semiconductor layer (22) free from the plurality of said at least second implanted regions (D1), carrying out a thermal diffusion step so that the plurality of implanted regions (D1) form a plurality of electrically continuous implanted column regions (D).