Semiconductor Power Device with Single In-Line Lead Module

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Solution Overview

Problem

Conventional semiconductor power devices with metal-oxide semiconductor field-effect transistor (MOSFET) chips in separate packages require excessive space and time for board-level mounting due to the need for separate pick-and-place processes and generate excessive impedance from board-level interconnection.

Innovation Solution

A semiconductor power device with semiconductor chip stacks, including a high-side MOSFET chip, a low-side MOSFET chip, and a clip connecting the source pad of the high-side chip to the drain pad of the low-side chip, integrated into a lead frame unit with a molding encapsulation, reducing the number of pick-and-place processes and enhancing space and time efficiency during board-level mounting.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Temperature

If MOSFET chips are placed side-by-side in separate packages, then heat dissipation is improved, but board-level mounting space and time efficiency deteriorate

Engineering Contradiction:
Improveheat dissipationVSAvoidboard-level mounting efficiency
Core Design Contradiction:
TemperatureVSProductivity

Solution Approach 1:

The patent combines multiple MOSFET chips (high-side and low-side) into a single integrated power module package, eliminating the need for separate pick-and-place processes for each chip. This merging approach maintains thermal management capabilities while dramatically improving board-level mounting efficiency by reducing the number of discrete components and assembly steps.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent implements a stacked chip architecture where high-side and low-side MOSFET chips are vertically stacked and interconnected through clips within the same package. This nesting approach allows multiple functional chips to occupy a compact three-dimensional space, improving space efficiency on the PCB while maintaining proper thermal dissipation paths for each chip.

Inventive Principle:
Principle #7Nested doll (Nesting)

2Adaptability or versatility

If separate pick-and-place processes are used for each package, then manufacturing flexibility is improved, but manufacturing time and complexity deteriorate

Engineering Contradiction:
Improvemanufacturing flexibilityVSAvoidpick-and-place process complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent integrates multiple MOSFET chips into a single pre-assembled power module with internal clip interconnections. This merging reduces the number of discrete pick-and-place operations required during manufacturing, simplifying the overall assembly process while maintaining the ability to select different module configurations based on application requirements.

Inventive Principle:
Principle #5Merging (Combining)

3Adaptability or versatility

If board-level interconnection is used for separate packages, then design flexibility is improved, but impedance deteriorates

Engineering Contradiction:
Improvedesign flexibilityVSAvoidimpedance
Core Design Contradiction:
Adaptability or versatilityVSObject-affected harmful factors

Solution Approach 1:

The patent integrates high-side and low-side MOSFET chips into a single package with internal clip interconnections, eliminating the need for lengthy board-level interconnections. This merging dramatically reduces parasitic inductance and impedance in the power path, while the module-level design still provides sufficient flexibility for various circuit configurations.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS9966328B2Semiconductor power device having single in-line lead module and method of making the same
Publication Date: 2018.05.08 ALPHA & OMEGA SEMICONDUCTOR (CAYMAN) LTD
  • US9966328B2 patent drawing
  • US9966328B2 patent drawing
  • US9966328B2 patent drawing

AI summary

A semiconductor power device is disclosed. The semiconductor power device comprises a lead frame unit, two or more pluralities of single in-line leads, two or more semiconductor chip stacks, and a molding encapsulation. Each semiconductor chip stack includes a high-side semiconductor chip, a low-side semiconductor chip and a clip connecting a top surface of the high-side semiconductor chip to a bottom surface of the low-side semiconductor chip. This invention further discloses a method for fabricating semiconductor power devices. The method comprises the steps of providing a lead frame strip having a plurality of lead frame units; providing two or more pluralities of single in-line leads; attaching two or more high-side semiconductor chips to each lead frame unit; connecting each of the two or more high-side semiconductor chips to a respective lead by a respective clip of two or more first clips; attaching a respective low-side semiconductor chip of the two or more low-side semiconductor chips to each clip of the two or more first clips; molding an encapsulation; and singulating the lead frame strip and the encapsulation to form the semiconductor power devices.