Semiconductor Power Device Spacer Silicide On-Resistance
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Solution Overview
Problem
Conventional semiconductor power devices face a trade-off between reducing on-resistance and maintaining breakdown voltage, as increasing carrier concentration in the drift region to lower on-resistance often results in a lower breakdown voltage.
Innovation Solution
A manufacturing method for a semiconductor power device that involves forming a spacer covering the sidewall of a gate stacked structure and performing a self-aligned silicide process to reduce the distance between the silicide layer and the channel region, thereby decreasing on-resistance without compromising breakdown voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the carrier concentration in the drift region is increased to reduce on-resistance, then the on-resistance decreases, but the breakdown voltage decreases
Solution Approach 1:
The source region is divided into two parts: a first source region connected to the body region and channel, and a second source region connected to the gate stacked structure. This segmentation allows independent optimization of each source region's function, enabling the first source region to maintain low on-resistance while the second source region supports breakdown voltage through its specific doping concentration and depth
Solution Approach 2:
Different regions are assigned different doping concentrations to optimize local properties. The first source region has a first doping concentration optimized for low on-resistance, while the second source region has a second doping concentration optimized for breakdown voltage. This local quality differentiation resolves the contradiction between low on-resistance and high breakdown voltage
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively reduces the on-resistance of the semiconductor power device by shortening the distance between the silicide layer and the channel region, while maintaining or improving breakdown voltage, thus enhancing the device's performance.
Implementation Method 1
A self-aligned silicide process with the spacer and the gate stacked structure functioning as a mask is performed so as to form a silicide layer at the exposed portion of the source region
Data Source
AI summary
A semiconductor power device and a manufacturing method thereof are provided. In the manufacturing method, before the self-aligned silicide process is performed, a gate stacked structure and a spacer are formed on a semiconductor layer having a body region and a source region. The spacer defines a portion of the source region for forming a silicide layer. Subsequently, the self-aligned silicide process is performed with the gate stacked structure and the spacer functioning as a mask to form the silicide layer at the defined portion of the source region. Thereafter, an interconnection structure including an interlayer dielectric layer and a source conductive layer is formed on the semiconductor layer. The source conductive layer is electrically connected to the source region. The silicide layer extends toward the gate stacked structure from a position under the source conductive layer to another position under the interlayer dielectric layer.