Semiconductor Power Device With Through-Conductive Tracks
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Solution Overview
Problem
Existing semiconductor power devices face limitations in conducting high currents efficiently due to large gaps between conductive areas, leading to increased resistance, self-inductance, and reduced heat conduction, which limits their maximum performance.
Innovation Solution
A semiconductor power device design featuring a first and second substrate with patterned electrically conductive layers and an independent electrically conductive track isolated by a dielectric material, allowing for optimized high current conduction without interruptions and enhanced heat transfer, while minimizing the device's thickness and parasitic effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate electrically conductive areas are isolated by a large gap to conduct high currents, then current conduction capability is improved, but resistance and self-inductance increase
Solution Approach 1:
The patent divides the electrically conductive area into a through-conductive area extending through the entire thickness of the substrate and separate contact areas on the front side. This segmentation allows the through-conductive area to provide a continuous low-resistance path for high currents while the contact areas can be optimally positioned and sized for current conduction without requiring large isolation gaps.
Solution Approach 2:
The patent transitions from a two-dimensional planar conductive area to a three-dimensional structure by creating a through-conductive area that extends vertically through the substrate thickness. This dimensional change enables the conductive path to maintain electrical continuity across the substrate without requiring large horizontal gaps for isolation, thereby reducing resistance and self-inductance while maintaining current conduction capability.
2Reliability
If the layer thickness is increased to conduct high currents, then current conduction is improved, but the gaps between conductive areas must be wider
Solution Approach 1:
The conductive structure is segmented into a through-conductive area that provides vertical current conduction through the substrate and separate contact areas on the front surface. This segmentation eliminates the need for large horizontal gaps between conductive areas, as the through-conductive area maintains electrical continuity vertically without requiring isolation gaps proportional to layer thickness.
Solution Approach 2:
The patent moves the conductive path from a purely horizontal plane to a vertical dimension by creating through-conductive areas that extend through the substrate thickness. This allows current conduction to be achieved through the thickness dimension rather than requiring increased horizontal gap widths, effectively decoupling current conduction capability from gap width requirements.
3Ease of operation
If transistors are made larger to accommodate the gap distance, then emitter-gate distance is improved, but device area increases
Solution Approach 1:
The conductive structure is segmented into through-conductive areas and separate contact areas, allowing the transistor components (emitter, gate, collector) to be positioned optimally without being constrained by large isolation gaps. The through-conductive area provides necessary electrical connections without requiring increased transistor dimensions.
Solution Approach 2:
By utilizing the vertical dimension with through-conductive areas extending through the substrate, the patent enables optimal positioning of transistor components in the horizontal plane without being forced to increase transistor area to accommodate gap distances. The electrical connections are achieved through the thickness dimension rather than requiring increased horizontal spacing.
4Loss of energy
If more interconnect structures are used between emitter and conductive area, then resistance is reduced, but device complexity increases
Solution Approach 1:
The conductive system is segmented into through-conductive areas that provide direct vertical pathways for current flow. This segmentation creates natural, low-resistance current paths through the substrate without requiring complex interconnect structures with multiple layers and connections, thereby reducing resistance while maintaining structural simplicity.
Solution Approach 2:
The patent utilizes the vertical dimension by creating through-conductive areas that extend through the substrate thickness. This provides direct, short current paths with low resistance without requiring multiple horizontal interconnect layers or complex routing structures, achieving low resistance through dimensional optimization rather than increased structural complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enables low resistance and self-inductance, allowing for higher maximum performance and efficient heat transfer, thereby improving the overall performance of the semiconductor power device.
Implementation Method 1
The layer of the dielectric material isolates the electrically conductive track from the patterned electrically conductive layer on which the stack is provided
Implementation Method 2
efficient heat transfer, thereby improving the overall performance of the semiconductor power device
Data Source
AI summary
Some embodiments relate to a semiconductor power device that includes a first substrate, a second substrate, a stack and an interconnect structure. The first substrate includes a first patterned electrically conductive layer on a first surface and a switching semiconductor element. The second substrate includes a second surface facing the first surface and a second patterned electrically conductive layer on the second surface. The stack includes an electrically conductive track and a layer of a dielectric material. The layer of the dielectric material is provided on the first or second patterned electrically conductive layer and the layer of the dielectric material isolates the electrically conductive track from the patterned electrically conductive layer on which the stack is provided. The interconnect structure provides at least one electrical connection electrically conductive layers or areas of the substrates.