Semiconductor Power Domain Layout With Isolation Dummy Gates

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Solution Overview

Problem

Semiconductor devices with cells of different voltages face challenges in increasing routing costs and deteriorating power consumption due to the integration of high and low voltage cells.

Innovation Solution

The implementation of isolation dummy gates to electrically isolate active regions in semiconductor devices, allowing for the adjustment of active region lengths in P-type and N-type FETs, and the use of hybrid power domains with different voltage levels to reduce power consumption and improve routing efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If high voltage cells are integrated to enable high performance computing, then computing speed is improved, but power consumption increases

Engineering Contradiction:
Improvecomputing speedVSAvoidpower consumption
Core Design Contradiction:
SpeedVSUse of energy by moving object

Solution Approach 1:

The semiconductor device is divided into multiple power domains with different voltage levels. High voltage power domains are used for performance-critical circuits requiring high computing speed, while low voltage power domains are used for less critical circuits where power consumption is more important. This segmentation allows the device to achieve high performance where needed without unnecessarily consuming high power across the entire device.

Inventive Principle:
Principle #1Segmentation

2Use of energy by moving object

If multiple voltage levels are integrated in the same plane, then power consumption can be reduced, but routing complexity increases

Engineering Contradiction:
Improvepower consumptionVSAvoidrouting complexity
Core Design Contradiction:
Use of energy by moving objectVSDevice complexity

Solution Approach 1:

The patent introduces a vertical dimension by stacking multiple power domains at different heights (different z-coordinates) rather than placing them side-by-side in the same plane. This 3D stacking approach allows multiple voltage domains to coexist without increasing lateral routing complexity, as connections can be made through vertical vias between layers rather than through complex planar routing.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Productivity

If isolation dummy gates are used to electrically isolate active regions, then routing efficiency is improved, but device complexity increases

Engineering Contradiction:
Improverouting efficiencyVSAvoiddevice complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The isolation dummy gates serve multiple functions simultaneously: they electrically isolate active regions from each other, define the boundaries of power domains, and provide routing pathways for signal and power connections. By combining multiple functions into a single structural element, the overall device complexity is minimized while achieving effective isolation and efficient routing.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS12476189B2Semiconductor device and method of manufacturing the same
Publication Date: 2025.11.18 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12476189B2 patent drawing
  • US12476189B2 patent drawing
  • US12476189B2 patent drawing

AI summary

A semiconductor device and a method for manufacturing the semiconductor device are provided. The semiconductor device comprises a first electrical conductor, a second electrical conductor, a third electrical conductor, a plurality of metal features and a plurality of active regions. The first electrical conductor extends along a first direction and is electrically coupled to a first voltage. The second electrical conductor extends along the first direction and is electrically coupled to a second voltage. The second voltage is lower than the first voltage. The third electrical conductor extending along the first direction is electrically coupled to a third voltage and disposed between the first electrical conductor and the second electrical conductor. The metal features extend along a second direction perpendicular to the first direction and are formed above the first electrical conductor, the second electrical conductor and the third electrical conductor.