Semiconductor Power Gating With Backup Storage for Fast Wake-Up
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Solution Overview
Problem
Current semiconductor devices face challenges in reducing power consumption, especially in resting states, and optimizing the transition time and energy required to return to normal operating states, which is crucial for advanced communication systems like 5G technology.
Innovation Solution
A semiconductor device incorporating a power supply circuit, a power management unit, and an arithmetic processing circuit with a flip-flop circuit and a capacitor-based storage mechanism, utilizing an oxide semiconductor to retain data and manage power supply potentials, enabling power gating and voltage scaling to minimize energy usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If power supply is stopped to reduce power consumption in resting state, then power consumption is reduced, but data retention is lost and transition time increases
Solution Approach 1:
The patent applies preliminary action by transferring data from the first circuit to the second circuit before stopping power supply. The power management unit controls the timing of data transfer operations in advance, ensuring data is safely stored in the second circuit before power gating occurs, thus preventing data loss and enabling faster recovery.
Solution Approach 2:
The patent introduces a second circuit as an intermediary storage mechanism between the first circuit and the power supply stoppage. This intermediate circuit retains data during the power-off period, acting as a buffer that preserves information while allowing the main arithmetic processing circuit to be powered down, thereby reducing power consumption without complete data loss.
2Use of energy by moving object
If power supply is stopped to reduce power consumption, then power consumption is reduced, but energy required for transition increases
Solution Approach 1:
The power management unit performs preliminary data transfer operations before power supply stoppage, preparing the system in advance. By transferring data to the second circuit beforehand, the system minimizes the energy required during the actual power-on transition, as no intensive data recovery operations are needed when power is restored.
3Speed
If data is retained in first circuit during power supply, then processing speed is maintained, but power consumption increases
Solution Approach 1:
The patent segments the storage function into two separate circuits: the first circuit for active data storage during operation, and the second circuit for data retention during power-off periods. This segmentation allows the system to maintain processing speed when needed while enabling power savings by transferring data to the second circuit during resting states.
Solution Approach 2:
The system employs periodic action by alternating between two operational modes: during active periods, data is stored in the first circuit for fast processing; during resting periods, power supply is stopped and data is transferred to the second circuit for retention. This periodic switching between modes optimizes the balance between processing speed and power consumption.
Data Source
AI summary
Power consumption is reduced. A semiconductor device includes an arithmetic processing circuit, a power supply circuit, a power management unit (PMU), and a power switch. The arithmetic processing circuit includes a storage circuit retaining generated data. The storage circuit includes a backup circuit including a transistor and a capacitor. When a control signal for transition to a resting state is input from the arithmetic processing circuit, the PMU performs voltage scaling operation for lowering a power supply potential of the arithmetic processing circuit. When the period of the resting state exceeds the set time, the PMU performs power gating operation for stopping power supply to the arithmetic processing circuit. Data saving operation of the storage circuit is performed before the voltage scaling operation.