Semiconductor Power Gating with Shielding Lines for Testing
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Solution Overview
Problem
The increasing number of circuit blocks in semiconductor devices leads to a higher frequency of testing, which increases the time required to detect failures, and there is a demand for reduced power consumption due to higher operating frequencies and miniaturization, necessitating a technique to manage power supply effectively.
Innovation Solution
The semiconductor device incorporates a power-gating technique with shielding lines between lead-out lines to reduce power consumption and simplify the detection of short circuits by applying different potentials to test pads, allowing for simultaneous testing of power supply lines and reducing the frequency of testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the number of circuit blocks is increased, then the functionality and performance of the semiconductor device are improved, but the number of power supply lines increases and the testing frequency increases, resulting in increased testing time
Solution Approach 1:
The patent segments the power supply testing by introducing shielding lines that electrically divide the power supply network into isolated regions. Each region can be tested independently by applying different potentials, allowing parallel testing of multiple circuit blocks rather than sequential testing, thus reducing total testing time while maintaining the ability to handle increased functionality
Solution Approach 2:
The shielding lines act as intermediary elements between power supply lines and circuit blocks. These shielding lines are selectively connected to different potentials (VDD, VSS, or floating) to create isolated testing regions, enabling the testing system to manage and test multiple circuit blocks efficiently without requiring proportional increases in testing frequency for each block
2Speed
If the operating frequency is increased and miniaturization is implemented, then the performance is improved, but the power consumption increases
Solution Approach 1:
The patent implements dynamic power management by selectively applying different potentials to shielding lines based on the operational state of circuit blocks. When circuit blocks are not in use or are in low-power mode, the shielding lines isolate them from active power supply, enabling dynamic power gating that reduces overall power consumption while maintaining high operating frequencies for active blocks
Solution Approach 2:
The shielding lines create locally differentiated power supply regions where different circuit blocks can operate with different power states simultaneously. This local quality control allows individual circuit blocks to be powered on or off independently, enabling precise power management that matches the actual operational requirements of each block
3Productivity
If shielding lines are provided between lead-out lines, then the detection of short circuits is simplified and testing efficiency is improved, but the device complexity increases
Solution Approach 1:
The shielding lines serve multiple functions simultaneously: they provide electromagnetic shielding, act as power gating control elements, enable isolated testing regions, and facilitate short circuit detection. This multi-functionality allows the same structural elements to address multiple concerns without proportionally increasing device complexity
Solution Approach 2:
The patent merges the shielding function with the power supply control function by using the same conductive structures (shielding lines) for both purposes. Rather than adding separate shielding structures and separate power gating mechanisms, the design combines these functions into a unified structure that reduces overall complexity while achieving both shielding and power management objectives
Data Source
AI summary
A semiconductor device includes a first circuit block, a second circuit block, a first lead-out line coupled to the first circuit block, a second lead-out line coupled to the second circuit block, a first pad coupled to the first lead-out line, a second pad coupled to the second lead-out line, and a shielding line provided between the first lead-out line and the second lead-out line.