Semiconductor Power Line Overlap Reduces Impedance
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Solution Overview
Problem
Current semiconductor devices with multiple chips connected through a wiring substrate face challenges in improving data processing capacity and signal transmission rates due to limitations in power supply efficiency and high-speed signal transmission, particularly with increased current demands and high impedance issues.
Innovation Solution
The electronic device incorporates a semiconductor device with multiple semiconductor chips mounted on a wiring substrate, where power lines and signal transmission paths are optimized by increasing the cross-sectional area of power supply paths and routing power lines to overlap with the logic chip, reducing impedance and heat generation, and using a stripline structure to control electromagnetic interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the current value supplied to the arithmetic processing circuit is increased to increase data processing capacity, then the data processing capacity is improved, but the impedance and heat generation increase
Solution Approach 1:
The power line is extended into the region overlapping the logic chip when viewed in plan view, utilizing the third dimension (vertical overlap) to increase the effective cross-sectional area of the power supply path without increasing the planar footprint. This dimensional transition allows more current to be supplied while reducing current density and heat generation per unit area.
Solution Approach 2:
The power line is pre-routed to overlap with the logic chip region before signal transmission begins, establishing optimal power supply paths in advance. This preliminary positioning ensures that when high current is needed for increased data processing, the power delivery infrastructure is already in place to handle the load with minimal impedance and heat generation.
2Productivity
If the current value supplied to the arithmetic processing circuit is increased to increase data processing capacity, then the data processing capacity is improved, but the impedance increases
Solution Approach 1:
By extending the power line into the overlapping region with the logic chip in the vertical dimension, the effective cross-sectional area for current flow is increased. This reduces the electrical impedance of the power supply path, allowing higher current values to be supplied to the arithmetic processing circuit with improved reliability and signal integrity.
3Productivity
If multiple semiconductor chips are mounted side by side on a wiring substrate, then the data processing capacity is improved, but the power supply efficiency deteriorates
Solution Approach 1:
The power line configuration utilizes vertical overlap in the third dimension to increase the effective power delivery area without increasing planar chip area. This allows efficient power distribution to multiple chips mounted side by side, maintaining power supply efficiency while supporting increased data processing capacity through multi-chip architecture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the electrical characteristics of the semiconductor device by improving power supply efficiency, reducing temperature rise, and stabilizing circuit operation, thereby increasing data processing capacity and signal transmission rates.
Implementation Method 1
the first wiring substrate includes a first power line which supplies a first power potential to each of the plurality of first semiconductor chips and a second power line which supplies a second power potential to the second semiconductor chip
Implementation Method 2
routing power lines to overlap with the logic chip, reducing impedance and heat generation
Data Source
AI summary
An electronic device includes a first wiring substrate and a semiconductor device mounted on the first wiring substrate. A plurality of first semiconductor chips and a second semiconductor chip which controls each of the plurality of first semiconductor chips are mounted side by side on a second wiring substrate of the semiconductor device. Further, the plurality of first semiconductor chips are mounted between a first substrate side of the wiring substrate and an extension line of a first chip side of the second semiconductor chip. Furthermore, the first wiring substrate includes a first power line which supplies a first power potential to each of the plurality of first semiconductor chips and a second power line which supplies a second power potential to the second semiconductor chip and has a width larger than that of the first power line. Also, the second power line intersects the first substrate side of the second wiring substrate and extends from a side of the first substrate side of the second wiring substrate toward the second semiconductor chip when seen in a plan view.