Semiconductor Power Line Reinforcement via Multi-Layer Routing
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Solution Overview
Problem
Recent advancements in semiconductor integrated circuits, characterized by finer sizes and reduced power supply voltage, lead to increased wiring resistance, reduced electrostatic discharge (ESD) resistance, and destabilization of circuit operations, necessitating a solution to strengthen power supply lines without increasing the device area.
Innovation Solution
The semiconductor integrated circuit device incorporates an IO region with power supply lines extending along the periphery, featuring low and high power supply voltage regions, where power supply lines protrude into the core region and are reinforced by additional lines in the wiring layer, effectively connecting and strengthening the power supply lines without requiring new lines in the core region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If power supply lines are mutually connected inside IO cells and internal-circuit power supply lines are connected, then power supply lines are strengthened, but wiring resources in the core region are required for both VDD and VSS lines, resulting in increase in device area
Solution Approach 1:
The patent utilizes multiple wiring layers to route power supply lines. Specifically, VDD lines are routed in one layer while VSS lines are routed in another layer, allowing both power supply lines to coexist without requiring additional core region area. This dimensional approach (using vertical layering) resolves the contradiction by enabling strengthened power supply connections without increasing the horizontal device footprint.
2Productivity
If device size becomes finer, then integration density increases, but wiring resistance increases and power supply voltage drops
Solution Approach 1:
The patent segments the power supply network into multiple parallel paths by providing separate VDD and VSS lines in different wiring layers. This segmentation allows current to be distributed across multiple parallel conduits, reducing the effective resistance and preventing voltage drops even as device dimensions scale down and individual wiring paths become narrower.
3Loss of energy
If power supply voltage is reduced, then power consumption decreases, but ESD resistance decreases and circuit operation becomes unstable
Solution Approach 1:
The patent employs a composite wiring structure using multiple materials and layers for power supply distribution. By combining copper or aluminum wiring in multiple layers with appropriate via connections, the structure achieves low resistance for power delivery while maintaining high ESD protection capability through the multi-layer architecture that can handle surge currents effectively.
Data Source
AI summary
A semiconductor integrated circuit device includes a core region and an IO region on a chip. In an IO cell row placed in the IO region, a first power supply line extending in the X direction in a low power supply voltage region has a portion protruding to the core region. A signal IO cell has a reinforcing line that connects a second power supply line extending in the X direction in the low power supply voltage region and a third power supply line extending in the X direction in a high power supply voltage region, the reinforcing line extending in the Y direction in a layer above the second and third power supply lines.