Semiconductor Power Line Resonance Suppression via Extraction
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Solution Overview
Problem
Variations in power-supply voltage due to impedance in power lines can degrade the operation characteristics of semiconductor devices and electronic equipment.
Innovation Solution
Incorporating a resistance element and a capacitance element connected between a terminal and the power line, along with a capacitance element between the terminal and a ground terminal, to suppress resonance phenomena and voltage variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If capacitance elements are added within the semiconductor chip to suppress resonance, then operation characteristics are improved, but chip area and manufacturing cost increase
Solution Approach 1:
The capacitance element is extracted from the semiconductor chip and placed on the package substrate instead. This allows the chip area to be reduced while still maintaining the resonance suppression function through the external capacitance element connected to the power line.
2Reliability
If additional capacitance elements are integrated within the chip, then resonance suppression is achieved, but manufacturing cost increases
Solution Approach 1:
The capacitance element is moved from the chip interior to the package substrate, eliminating the need for complex integration processes and reducing manufacturing costs while maintaining resonance suppression capability.
Solution Approach 2:
The power supply system is segmented into internal chip components and external package components. The capacitance element is placed in the external package area, allowing separate optimization of chip design and package design, thereby reducing overall manufacturing complexity and cost.
3Device complexity
If impedance of power line is not adjusted, then chip design is simplified, but power-supply voltage varies degrading operation characteristics
Solution Approach 1:
A resistance element is introduced as an intermediary component between the power line and ground on the package substrate. This resistance element adjusts the impedance of the power line, stabilizing the power-supply voltage without requiring complex internal chip design modifications.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces the impedance peak value on the power line, thereby stabilizing the operation characteristics of semiconductor devices and preventing degradation due to resonance and noise-related issues, without increasing the chip size or manufacturing costs.
Implementation Method 1
a first capacitance element connected between the second terminal and a ground terminal
Implementation Method 2
a resistance element connected between the second terminal and the power line
Data Source
AI summary
A semiconductor device includes an input/output circuit to which a signal is input or from which a signal is output; a first terminal connected to a power line of the input/output circuit; a second terminal connected to the power line; a resistance element connected between the second terminal and the power line; and a first capacitance element connected between the second terminal and a ground terminal. The semiconductor device can suppress a resonance phenomena and Volt age variation caused by impedance of the power line.