Semiconductor Power Mesh with Overlapping Lines
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Solution Overview
Problem
The resistance of the power mesh in semiconductor devices increases due to the width reduction of power lines and power straps, leading to unstable operation and potential malfunctions, which affects the performance characteristics of the device.
Innovation Solution
The power mesh is designed with power lines and power straps that have a reduced width only in sections where they overlap, maintaining the same width as the lane in non-overlapping sections, and are coupled in metal line bottleneck sections to increase parallel coupling, thereby reducing the series resistance component.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the width of power lines and power straps is reduced to minimize area, then the area of the power mesh is reduced, but the resistance of the power mesh increases
Solution Approach 1:
The power lines and power straps have different widths in different sections: full width in non-overlapping sections and reduced width in overlapping sections. This local variation in geometry allows the structure to maintain low resistance where needed while minimizing area where possible.
Solution Approach 2:
The power lines and power straps are arranged to overlap and share lanes, with one structure nested within the spatial footprint of the other. This nesting allows two conductive paths to occupy the same physical space, reducing the total area required for the power mesh while maintaining adequate current carrying capacity through parallel paths.
2Volume of moving object
If the width of power lines and power straps is reduced to reduce device size, then the overall device footprint is reduced, but voltage drops increase due to higher resistance
Solution Approach 1:
Multiple power lines and power straps are merged into shared lanes where they overlap, creating parallel current paths. This merging allows the current to be distributed across multiple conductors, reducing the effective resistance and minimizing voltage drops while maintaining a compact device footprint.
Solution Approach 2:
The geometric parameters of the power lines and power straps are varied along their length, with width changing from full width to reduced width in overlapping sections. This parameter modification optimizes the balance between resistance and area by concentrating full-width sections where they provide the most benefit and using reduced-width sections where area is at a premium.
3Reliability
If power lines and power straps are coupled in bottleneck sections to increase parallel coupling, then the resistance is reduced, but the manufacturing complexity increases
Solution Approach 1:
The power mesh is segmented into distinct regions: non-overlapping sections where lines maintain full width, overlapping sections where width is reduced, and bottleneck sections where coupling occurs. This segmentation allows for systematic manufacturing by defining clear zones with different geometric characteristics that can be processed in a standardized sequence.
Data Source
AI summary
A semiconductor device includes an internal circuit and a power mesh configured to transmit an operating voltage to the internal circuit. The power mesh includes first power lines extending in a first direction and arranged in a second direction intersecting with the first direction, when viewed from a top; second power lines sharing lanes with the first power lines and at least partially overlapping with the first power lines in the second direction; first power straps extending in the second direction and coupled to the first power lines; and second power straps extending in the second direction and coupled to the second power lines. Each of the first and second power lines may have a width of the same size as a width of each lane in sections where they do not overlap, and may have a width of a size smaller than the width of each lane in sections where they overlap.