Semiconductor Power Delivery Network With Integrated Decoupling Capacitance
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Solution Overview
Problem
There is a growing demand for semiconductor devices with high reliability, high speed, and multifunctionality, which requires increasingly complex structures, but existing technologies struggle to efficiently integrate decoupling capacitors in a small space to enhance performance.
Innovation Solution
A semiconductor device is designed with a decoupling capacitor implemented using a power delivery network, featuring a semiconductor substrate with a channel pattern, source/drain patterns, a contact electrode, a lower wiring structure including metal lines and an auxiliary electrode, and through vias connecting these components, allowing for efficient power supply and improved performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If decoupling capacitors are integrated in a small space to enhance performance, then device performance and reliability are improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent combines the decoupling capacitor function with the power delivery network by using metal lines and auxiliary electrodes that are already part of the power distribution structure. The lower wiring structure includes metal lines for power supply and ground, with auxiliary electrodes positioned between them to form capacitive elements, merging the power delivery and decoupling functions into a single integrated system.
Solution Approach 2:
The lower wiring structure serves multiple functions: it provides power delivery through metal lines while simultaneously providing decoupling capacitance through auxiliary electrodes positioned between power and ground lines. This multi-functional design eliminates the need for separate capacitor components, reducing device complexity while maintaining performance.
2Area of stationary object
If decoupling capacitors are integrated in a small space, then area utilization is improved, but manufacturing precision requirements increase
Solution Approach 1:
The decoupling capacitor is segmented into distributed capacitive elements formed by auxiliary electrodes positioned between power and ground metal lines throughout the lower wiring structure. This segmentation allows the capacitor function to be distributed across multiple small elements rather than requiring a single large capacitor, reducing area while maintaining total capacitance and lowering individual manufacturing precision requirements.
Solution Approach 2:
The patent utilizes the vertical dimension by positioning auxiliary electrodes between metal lines in the lower wiring structure, creating capacitance in the third dimension rather than requiring additional planar area. This dimensional approach allows compact integration of decoupling capacitance within the existing power delivery network footprint.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The implementation of a decoupling capacitor using a power delivery network within the semiconductor device enhances performance by efficiently arranging wiring and improving capacitance, thereby addressing the need for complex and high-performance semiconductor devices.
Implementation Method 1
The auxiliary electrode may overlap an other of the first metal line and the second metal line in a state insulated from the other of the first metal line and the second metal line
Implementation Method 2
a through via penetrating the semiconductor substrate and connecting the contact electrode and the lower wiring structure to each other
Data Source
Figure 1
Figure 2
Figure 3A
AI summary
A semiconductor device may include a semiconductor substrate (100), a channel pattern (CH) on a first surface (100a) of the semiconductor substrate (100), source/drain patterns (SD) on the first surface (100a) of the semiconductor substrate (100) and on both sides of the channel pattern (CH), a contact electrode (CT1; CT1') electrically connected to the source/drain patterns (SD), a lower wiring structure (400) on the second surface (100b) of the semiconductor substrate (100), and a through via (210; 210') penetrating the semiconductor substrate (100) and connecting the contact electrode (CT1; CT1') and the lower wiring structure (400) to each other. The lower wiring structure (400) may include a first metal line (510) connected to a first voltage, a second metal line (520) connected to a second voltage, and an auxiliary electrode (530) electrically connected to one of the first metal line (510) and the second metal line (520). The auxiliary electrode (530) may overlap and be insulated from an other of the first metal line (510) and the second metal line (520).