Semiconductor Device Sudden Power-Off Detection Circuit

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Solution Overview

Problem

Nonvolatile semiconductor memory devices face data reliability issues during program, read, or erasing operations when external power source voltage is not smoothly supplied, leading to unintended voltage level changes that can damage data distribution in memory cells.

Innovation Solution

A semiconductor device with a sudden power detection circuit generating a power-off control signal based on external power source voltage levels, an internal voltage generation circuit driving internal power as external power during power-off, and discharging circuits for bit, source, and word lines to ensure stable operations in sudden power-off states.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If high voltage is applied to word line, bit line or source line during program, read or erasing operations, then data storage and processing can be performed, but if external power source voltage is not smoothly supplied, the voltage level may be unwillingly lowered causing data distribution to be influenced and reliability to deteriorate

Engineering Contradiction:
Improvedata processing speedVSAvoiddata reliability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The sudden power detection circuit performs preliminary detection of power source voltage abnormalities before they cause data damage. By detecting voltage level changes in advance during program, read, or erasing operations, the system can trigger protective measures (discharging specific nodes) before the unwanted voltage lowering affects memory cell data distribution, thus preventing reliability deterioration while maintaining high-speed operation capability

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The discharging circuit performs preliminary anti-action by actively discharging specific nodes when sudden power-off is detected. This counteracts the unwanted voltage lowering effect by controlling the discharge timing and path, preventing the voltage level changes that would otherwise distort data distribution in memory cells, thereby protecting data reliability during high-voltage operations

Inventive Principle:
Principle #9Preliminary anti-action

2Adaptability or versatility

If external power source voltage is not smoothly supplied during program, read or erasing operations, then power supply instability occurs, but this causes voltage level to be unwillingly lowered which influences data distribution and damages stored data

Engineering Contradiction:
Improvepower supply adaptabilityVSAvoidvoltage level fluctuation
Core Design Contradiction:
Adaptability or versatilityVSObject-affected harmful factors

Solution Approach 1:

The sudden power detection circuit acts as an intermediary between the external power source and the memory cell array. It monitors the power source voltage and detects abnormalities, serving as a buffer that isolates the memory cells from direct voltage fluctuations. When instability is detected, it triggers the discharging circuit to compensate, thus mediating the harmful effect of voltage level changes on data distribution

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The system performs self-service by automatically detecting power source abnormalities and initiating protective discharging operations without external intervention. The sudden power detection circuit continuously monitors the power supply status and autonomously activates the discharging circuit when voltage instability is detected, enabling the system to protect itself from data damage caused by power supply fluctuations during critical operations

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS11315608B2Semiconductor device and semiconductor memory device
Publication Date: 2022.04.26 SK HYNIX INC
  • US11315608B2 patent drawing
  • US11315608B2 patent drawing
  • US11315608B2 patent drawing

AI summary

A semiconductor device may include a sudden power detection circuit and an operation circuit. The sudden power detection circuit may generate a power-off control signal in a sudden power-off state. The operation circuit may discharge a specific node based on the power-off control signal.