Semiconductor Power Rail Insulation via Gate Contact
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Solution Overview
Problem
The integration of semiconductor devices is compromised due to weakened stress in source/drain layers when gate structures at the boundary area between neighboring standard cells are removed, leading to reduced electrical isolation.
Innovation Solution
A semiconductor device design that includes a substrate with cell regions and a power rail region, where a gate structure extends from the boundary area between cell regions to the power rail region, and a contact plug connects the power rail to the gate structure, allowing for the supply of a turn-off signal to electrically insulate the cell regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gate structures at boundary areas between neighboring standard cells are removed for electrical isolation, then electrical isolation between cells is improved, but stress applied to source/drain layers adjacent the gate structures is weakened
Solution Approach 1:
The gate structure is segmented into two parts: a first gate structure in the first standard cell and a second gate structure in the second standard cell. These segmented gate structures are positioned adjacent to each other at the boundary area, allowing each cell to maintain its own gate structure for stress application while still achieving electrical isolation between the cells through the boundary configuration.
Solution Approach 2:
Instead of removing gate structures at boundary areas to achieve electrical isolation (conventional approach), this invention inverts the approach by maintaining gate structures at the boundary and using their adjacent positioning to achieve both electrical isolation and stress application. The gate structures are kept but configured to serve dual purposes.
2Reliability
If one gate structure is formed at an edge of each of neighboring standard cells and removed, then electrical isolation is achieved, but the integration degree of the semiconductor device decreases due to the areas of the gate structures
Solution Approach 1:
The first gate structure and the second gate structure are merged or positioned adjacent to each other at the boundary area between the first and second standard cells. This merging configuration allows the gate structures to serve dual purposes: maintaining electrical isolation between cells while minimizing the area occupied, thereby preserving high integration degree.
Data Source
AI summary
A semiconductor device is provided including a substrate, a first gate structure, a first contact plug and a power rail. The substrate includes first and second cell regions extending in a first direction, and a power rail region connected to each of opposite ends of the first and second cell regions in a second direction. The first gate structure extends in the second direction from a boundary area between the first and second cell regions to the power rail region. The first contact plug is formed on the power rail region, and contacts an upper surface of the first gate structure. The power rail extends in the first direction on the power rail region, and is electrically connected to the first contact plug. The power rail supplies a turn-off signal to the first gate structure through the first contact plug to electrically insulate the first and second cell regions.