Semiconductor Device Power Rail Penetration Via Integration
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Solution Overview
Problem
The scaling down of metal-oxide-semiconductor field-effect transistors (MOS-FETs) in semiconductor devices leads to deterioration in operational properties, necessitating a solution for high integration density and improved electric characteristics.
Innovation Solution
A semiconductor device design featuring a semiconductor substrate with transistors, power rails, interconnection lines, and capacitors, where penetration vias connect the interconnection lines to the power rail and capacitors are placed between them, enhancing integration density and electric characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If MOS-FETs are scaled down to increase integration density, then the number of transistors per unit area increases, but operational properties deteriorate
Solution Approach 1:
The patent introduces a third dimension by forming protruding active regions that extend vertically from the semiconductor substrate surface. This allows the channel length to be effectively increased in the vertical direction while maintaining a compact planar footprint, thereby improving transistor operational properties without sacrificing integration density. The protruding structure creates an additional spatial dimension for carrier transport, enabling better device performance at scaled dimensions.
2Quantity of substance
If more transistors are integrated in a given area, then integration density increases, but power delivery and decoupling become more challenging
Solution Approach 1:
The patent segments the power delivery function by introducing separate penetration vias dedicated to power rail connections and distinct lower interconnection lines for signal routing. This segmentation allows independent optimization of power delivery paths and signal interconnection paths, reducing interference and simplifying the power delivery network design in high-density integrated circuits.
Solution Approach 2:
The patent introduces capacitors as intermediary elements connected between the lower interconnection lines and ground. These capacitors serve as local energy storage and decoupling elements, mediating between the power delivery network and the transient current demands of densely packed transistors, thereby stabilizing power supply without increasing overall network complexity.
3Productivity
If penetration vias are used to connect lower interconnection lines to power rails, then vertical interconnection efficiency improves, but manufacturing complexity increases
Solution Approach 1:
The patent merges the formation of penetration vias with the existing via formation process used for connecting gate electrodes to interlayer insulating layers. By using the same via formation methodology for both purposes, the manufacturing process complexity is minimized while achieving efficient vertical interconnection between lower interconnection lines and power rails.
Data Source
AI summary
A semiconductor device includes a semiconductor substrate having a first surface and a second surface opposite to the first surface; a transistor provided on the first surface of the semiconductor substrate; a power rail provided on the first surface of the semiconductor substrate and electrically connected to the transistor; first and second lower interconnection lines provided on the second surface of the semiconductor substrate and spaced apart from each other in a first direction perpendicular to the second surface of the semiconductor substrate; a penetration via penetrating the semiconductor substrate and connecting a corresponding one of the first and second lower interconnection lines to the power rail; and a capacitor provided between and electrically connected to the first and second lower interconnection lines.