Semiconductor Power Routing Patterns for Voltage Drop Reduction
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Solution Overview
Problem
Conventional semiconductor devices face challenges in providing stable power supply due to increased operating speeds, leading to reliability issues as they struggle to maintain consistent power levels, especially with the addition of supplemental wiring lines required for decoupling capacitors.
Innovation Solution
The semiconductor device incorporates internal wiring line patterns and power routing patterns aligned with virtual tracks, with the power routing patterns not coupled to vertical vias, to ensure stable power supply by reducing resistance and minimizing voltage drops, and additional power lines are placed directly over decoupling capacitors to enhance conductive paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If operating speed is increased, then performance is improved, but power stability deteriorates
Solution Approach 1:
The power supply network is segmented into multiple independent power routing patterns (first, second, third power routing patterns) that are distributed across different wiring line patterns. This segmentation allows each power routing pattern to independently serve specific active patterns, reducing the overall impact of voltage drops and improving power stability at high operating speeds.
Solution Approach 2:
Power routing patterns are strategically positioned to provide localized power supply to specific regions. The first power routing pattern is disposed over first active patterns, the second power routing pattern over second active patterns, and the third power routing pattern over third active patterns. This local quality approach ensures that each region receives optimized power supply, maintaining power stability even as operating speed increases.
2Reliability
If supplemental wiring lines are added for decoupling capacitors, then power stability is improved, but device complexity increases
Solution Approach 1:
The power routing patterns are designed to serve multiple functions simultaneously. They not only provide power supply to active patterns but also serve as decoupling capacitor wiring, eliminating the need for separate supplemental wiring lines. The first, second, and third power routing patterns collectively perform both power distribution and decoupling functions, reducing overall device complexity while maintaining power stability.
Solution Approach 2:
The invention merges the power supply function and decoupling capacitor function into a unified power routing structure. By combining these functions into the same wiring line patterns, the device avoids the complexity of separate wiring systems while achieving both power stability and decoupling effects.
3Manufacturing precision
If power routing patterns are aligned with virtual tracks, then manufacturing precision is improved, but manufacturing complexity increases
Solution Approach 1:
Virtual wiring line pattern tracks are pre-defined before the actual wiring line patterns are formed. These virtual tracks serve as guiding templates that determine the precise positioning of power routing patterns. By establishing the track layout in advance, the manufacturing process achieves high precision alignment without requiring complex real-time adjustment mechanisms, as the virtual tracks provide a straightforward framework for pattern formation.
Data Source
AI summary
A semiconductor device includes a substrate provided with a decoupling capacitor and plurality of circuit elements disposed along a first direction, and a plurality of first wiring line patterns disposed in a first wiring line layer over the substrate, including a power routing pattern coupled to the decoupling capacitor and a plurality of internal wiring line patterns coupled to the plurality of circuit elements. The plurality of first wiring line patterns extend in the first direction, and are aligned in conformity with virtual wiring line pattern tracks which are defined at a first pitch along a second direction intersecting the first direction and parallel to the substrate.