Semiconductor Power Supply Control with Segmented Switches
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Solution Overview
Problem
Conventional semiconductor integrated circuit devices experience large rush currents when transitioning from a power supply interception state to an operational state, which can generate power supply noise that affects other circuits.
Innovation Solution
The implementation of a semiconductor integrated circuit device with a configuration that includes multiple power supply switch units and transfer gates to divide the control line, providing sufficient RC delays and feedback control to suppress rush currents by gradually turning on transistors with different gate widths, thereby controlling the power supply voltage rise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single power supply switch is used to interrupt power supply, then the circuit structure is simple, but a large rush current is generated when returning from interception state to operation state
Solution Approach 1:
The power supply switch is divided into multiple switch transistors (first switch transistor and second switch transistor) connected in series. This segmentation allows the power supply voltage to be applied gradually through multiple stages rather than all at once, effectively reducing the rush current while maintaining a relatively simple overall structure.
2Object-generated harmful factors
If power supply switches are divided and turned on successively, then rush current is suppressed, but additional capacitors are required to control the delay time
Solution Approach 1:
The control signal line itself is utilized to provide the delay function through its inherent capacitance and resistance characteristics. The first control signal line receives the control signal and automatically generates the delayed second control signal through RC time constants formed by the line's parasitic capacitance and resistance, eliminating the need for external delay capacitors.
3Object-generated harmful factors
If capacitors are added to control delay time between switches, then rush current is suppressed, but chip area increases
Solution Approach 1:
The control signal transmission lines are designed to utilize their own parasitic capacitance and resistance to create the necessary delay effect. By carefully designing the line dimensions and materials, the required RC delay is achieved without adding external capacitor components, thereby avoiding additional chip area consumption.
4Speed
If power supply voltage rises quickly, then the circuit responds fast, but power supply noise is generated that affects other circuits
Solution Approach 1:
The power supply voltage application is segmented into multiple stages through series-connected switch transistors. The first switch transistor applies part of the voltage first, then the second switch transistor completes the voltage application after a controlled delay. This staged approach slows down the overall voltage rise, reducing electromagnetic interference and noise while still maintaining acceptable response speed for the circuit operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively suppresses rush currents, stabilizes power supply voltage transitions, and reduces chip area requirements, allowing for stable power supply without the need for additional capacitors.
Implementation Method 1
providing sufficient RC delays and feedback control to suppress rush currents by gradually turning on transistors
Implementation Method 2
gradually turning on transistors with different gate widths, thereby controlling the power supply voltage rise
Data Source
AI summary
A semiconductor integrated circuit device according to an embodiment includes at least one first transistor connected at its source to an input power supply line, connected at its drain to an output power supply line, and connected at its gate to a first control line, at least one second transistor connected at its source to the input power supply line, connected at its drain to the output power supply line, and connected at its gate to a second control line, a first buffer which drives the first control line, a second buffer configured to receive a control signal input via the first control line and drive the second control line, and a plurality of transfer gates provided to divide the first control line into a plurality of pieces, the plurality of transfer gates being capable of connecting pieces obtained by dividing the first control line.