Semiconductor Power Supply Path Layout for Effective Wiring Area

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Solution Overview

Problem

Existing semiconductor devices with multiple wiring layers and through holes face challenges in maintaining effective wiring area due to the reduction in power supply wiring area caused by through holes, leading to instability in power supply.

Innovation Solution

A semiconductor device configuration with a chip module and main substrate featuring inner and outer peripheral-side terminal groups, where power supply terminals are arranged to overlap the semiconductor chip, allowing for a short power supply path and reduced impedance, eliminating the need for through holes in the surface layer power supply path.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If through holes are provided to connect wiring layers, then electrical connection between wiring layers is enabled, but the effective area of power supply wiring is reduced

Engineering Contradiction:
Improveelectrical connection between wiring layersVSAvoideffective area of power supply wiring
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The invention transitions the power supply path from a two-dimensional planar layout to a three-dimensional stacked configuration. By providing through holes that penetrate the substrate and forming power supply wiring in both the first wiring layer (below substrate) and second wiring layer (above substrate), the power supply path extends in the thickness direction (third dimension). This dimensional transition allows the power supply wiring to bypass the through holes that connect signal wiring layers, thereby maintaining effective wiring area while enabling inter-layer electrical connections.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The power supply path is segmented into multiple sections located in different spatial regions. The power supply wiring is divided into a first power supply wiring in the first wiring layer and a second power supply wiring in the second wiring layer, connected via through holes. This segmentation allows different portions of the power supply path to be positioned in regions with different functional requirements, enabling the path to avoid areas occupied by signal through holes while maintaining continuity.

Inventive Principle:
Principle #1Segmentation

2Reliability

If wiring-removed regions are provided around through holes for signal transfer, then insulation between signal wiring and power supply wiring is maintained, but the area of power supply wiring is further reduced

Engineering Contradiction:
Improveinsulation between signal and power supply wiringVSAvoidarea of power supply wiring
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The invention resolves the insulation conflict by utilizing the third dimension (thickness direction). Instead of removing power supply wiring in the planar region around through holes (which would reduce effective area), the power supply wiring is routed through through holes that extend in the thickness direction. This allows power supply wiring to be positioned vertically above or below signal wiring regions, maintaining insulation without sacrificing planar wiring area.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Reliability

If power supply wiring is arranged regularly around through holes, then stable power supply is enabled, but the effective area of power supply wiring is reduced by the amount of wiring-removed regions

Engineering Contradiction:
Improvestable power supplyVSAvoideffective area of power supply wiring
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The power supply path is segmented into multiple sections located in different spatial regions. The power supply wiring is divided into a first power supply wiring in the first wiring layer and a second power supply wiring in the second wiring layer, connected via through holes. This segmentation allows different portions of the power supply path to be positioned in regions with different functional requirements, enabling the path to avoid areas occupied by signal through holes while maintaining continuity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The invention merges the power supply path with the through holes used for signal transfer. By forming power supply wiring inside or along the through holes (rather than around them), the same structural features serve dual purposes: signal transfer through the through holes and power supply along/through the same vertical pathways. This merging eliminates the need for separate wiring-removed regions, thereby maximizing effective power supply wiring area.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentEP3916778A1Semiconductor device, chip module, and semiconductor module
Publication Date: 2021.12.01 AISIN CORP
  • EP3916778A1 patent drawingFigure 1~2
  • EP3916778A1 patent drawingFigure 3
  • EP3916778A1 patent drawingFigure 4

AI summary

A technique that is capable of suppressing a decrease in the effective area of wiring due to through holes and enables stable power supply is provided. A semiconductor device (1) has a surface layer power supply path (40) in a surface layer wiring layer (31), on which a chip module (5M) is mounted, of a main substrate (3) that has a plurality of wiring layers (31, 32, 33, 39) and through holes (TH), the surface layer power supply path (40) supplying power to a semiconductor chip (51p) via an inner peripheral-side power supply terminal group (141g) and an outer peripheral-side power supply terminal group (16g). The surface layer power supply path (40) overlaps the inner peripheral-side power supply terminal group (141g) and the outer peripheral-side power supply terminal group (16g) as seen in the orthogonal direction (Z), and is formed continuously so as to extend in a direction (Y) from a position at which the surface layer power supply path (40) is connected to the inner peripheral-side power supply terminal group (141g) toward the outer peripheral side of the main substrate (3).