Semiconductor Device Synchronizing Power Supply Timings

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Solution Overview

Problem

The use of multiple display drivers for large or high-chroma display panels leads to voltage differences between display regions, causing luminance and gradation differences, and shifting power supply and discharge release timings between drivers results in through-current interference.

Innovation Solution

A semiconductor device with a power supply unit, drive unit, external interface unit, and control unit that synchronizes power supply and discharge release timings across multiple modes, delaying the supply start timing in the second mode to prevent through-current and reduce peak current.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If multiple display drivers are used to drive large or high-chroma display panels, then the display capability is improved, but voltage differences between display regions cause luminance and gradation differences

Engineering Contradiction:
Improvedisplay capabilityVSAvoidluminance consistency
Core Design Contradiction:
Adaptability or versatilityVSManufacturing precision

Solution Approach 1:

The patent merges the power supply lines of multiple display drivers through a common external power supply terminal. This ensures that all drivers receive the same operation power supply voltage, eliminating voltage differences between display regions and preventing luminance and gradation differences while maintaining the ability to drive large or high-chroma panels

Inventive Principle:
Principle #5Merging (Combining)

2Loss of energy

If power supply and discharge release timings are shifted between multiple drivers, then peak current is reduced, but through-current interference occurs

Engineering Contradiction:
Improvepeak currentVSAvoidthrough-current interference
Core Design Contradiction:
Loss of energyVSObject-generated harmful factors

Solution Approach 1:

The patent combines the power supply lines of multiple drivers into a common external power supply terminal and synchronizes the discharge release timing of all drivers. This ensures that discharge occurs simultaneously across all drivers, preventing through-current interference while the common power supply terminal manages peak current through unified power distribution

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The control unit monitors the operation state of multiple drivers and adjusts the discharge release timing based on feedback from the system state. This ensures synchronized discharge that prevents through-current interference while optimizing peak current management

Inventive Principle:
Principle #23Feedback

3Speed

If multiple drivers start power supply simultaneously, then system responsiveness is improved, but in-rush current increases and causes EMI and voltage drop

Engineering Contradiction:
Improvesystem responsivenessVSAvoidin-rush current
Core Design Contradiction:
SpeedVSObject-affected harmful factors

Solution Approach 1:

The control unit performs preliminary coordination of power supply timing for multiple drivers. Before simultaneously enabling power supply to all drivers, the system prepares the power distribution through the common external power supply terminal, ensuring that simultaneous startup does not cause excessive in-rush current while maintaining system responsiveness

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS10504478B2Semiconductor device having shifted operation voltages in different modes and electronic apparatus thereof
Publication Date: 2019.12.10 SYNAPTICS INC
  • US10504478B2 patent drawing
  • US10504478B2 patent drawing
  • US10504478B2 patent drawing

AI summary

A semiconductor device has a first mode in which the semiconductor device is used alone and a second mode in which the semiconductor device is used in combination with another semiconductor device. In case that one driven device is driven using the semiconductor device in the first mode and the second mode, power supply lines are caused to allow electrical conduction to each other outside of each semiconductor device in order to cancel errors of operation power supply voltages of each semiconductor device. In case that a power supply unit of each semiconductor device is operable by receiving an instruction for release of a low power consumption state, a supply start timing of the operation power supply voltages in the second mode is delayed as compared to that in the first mode.