Semiconductor Power Supply Wire Multilayer Electromigration Layout
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Solution Overview
Problem
In semiconductor integrated circuits, electromigration (EM) occurs due to high current densities, leading to wire breaks and increased worker-hours in power supply arrangement design, especially with process miniaturization reducing wire widths and terminal counts, and existing methods like broadening wires and increasing vias are insufficient.
Innovation Solution
The power supply wire between IO and ring power supplies is formed using a top layer with a high current threshold value, and the ring power supply is formed one level lower to prevent short circuits, while current density is uniformly distributed using multiple layers and vias, and the number and shape of contacts are optimized to avoid exceeding current threshold values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the wire width is broadened to reduce electromigration, then the current threshold value increases, but the wire area increases and process miniaturization is hindered
Solution Approach 1:
The patent transitions from a two-dimensional wire width expansion to a three-dimensional multi-layer structure. By stacking power supply wires across multiple layers (Mx, Mx-1, Mx-2) and using vias for vertical connections, the current path is distributed in the vertical dimension, effectively increasing the current threshold without increasing the planar wire area.
Solution Approach 2:
The power supply network is segmented into multiple layers with distinct functions. The top layer (Mx) carries high-current power supply wires, while lower layers (Mx-1, Mx-2) carry ring power supplies and signal lines. This segmentation allows optimized current distribution and prevents electromigration in critical paths without requiring uniform wire width increases throughout the entire network.
2Reliability
If the number of vias is increased to reduce electromigration, then the current threshold value increases, but the device complexity and worker-hours increase
Solution Approach 1:
The patent uses vertical via connections to distribute current in the third dimension. Instead of adding more vias in the same plane, the design creates a multi-layer via structure where vias connect different metal layers (Mx to Mx-1 to Mx-2), effectively increasing current capacity without proportionally increasing via count or complexity.
Solution Approach 2:
The multi-layer via structure concentrates enhanced current capability at critical electromigration-prone locations (power supply connections) rather than uniformly increasing via density throughout the entire circuit. This localized quality enhancement reduces overall device complexity while targeting specific reliability issues.
3Ease of manufacture
If power supply wires are arranged in mesh form with constant pitch, then the layout process is simplified, but current threshold values may be exceeded in certain regions
Solution Approach 1:
The patent maintains the simple mesh-like constant pitch arrangement in the planar direction while adding a vertical layer dimension to resolve current threshold issues. Power supply wires are distributed across multiple layers (Mx, Mx-1, Mx-2) with constant pitch within each layer, preserving layout simplicity while the vertical stacking provides additional current pathways.
Solution Approach 2:
The power supply network is segmented into multiple layers, each with its own mesh pattern. This segmentation allows the simple constant pitch rule to be applied independently to each layer, maintaining ease of manufacture while the combined multi-layer structure provides sufficient current capacity even in high-demand regions.
4Reliability
If the top layer is used for power supply wires with high current threshold, then electromigration is reduced, but short circuit risk with lower layer ring power supplies increases
Solution Approach 1:
The patent segments the power supply network into distinct layers with clear functional separation. The top layer (Mx) is dedicated to high-current power supply wires, while lower layers (Mx-1, Mx-2) contain ring power supplies and signal lines. This vertical segmentation physically isolates high-current paths from sensitive structures, reducing short circuit risk while maintaining high current threshold capability.
Solution Approach 2:
The design resolves the short circuit risk by moving conflicting structures into different vertical layers. Power supply wires that would otherwise be in the same plane as ring power supplies are placed on the top layer (Mx), while ring power supplies are on lower layers (Mx-1, Mx-2), using the vertical dimension to eliminate planar overlap and short circuit hazards.
Data Source
AI summary
In a layout process of a semiconductor integrated circuit, a power supply is initially formed in an arrangement in which the current threshold value is not exceeded. In a case where the excess over the current threshold value occurs after the power supply is formed, the power supply arrangement is changed according to the current threshold value, design rule data base, and power supply wiring density so as not to exceed the current threshold value.