Semiconductor Power Switch Control for Reset Stability

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Solution Overview

Problem

Semiconductor devices face challenges in efficiently managing power-down modes, particularly in maintaining power supply voltage during reset operations while minimizing power consumption and ensuring stable transitions between power-down and active modes without relying on clock enablement signals.

Innovation Solution

The semiconductor device incorporates an operation period signal generation circuit and a power switch control signal generation circuit to manage power supply voltage, maintaining it during reset operations and interrupting it during power-down modes, using logic level control signals to activate and deactivate buffer circuits accordingly.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If the semiconductor device interrupts the power supply voltage to activate power-down mode, then power consumption is reduced, but reset operations cannot be stably executed

Engineering Contradiction:

Improvepower consumptionVSAvoidreset operation stability

Core Design Contradiction:

Loss of energyVSReliability

Solution Approach 1:

The device is divided into multiple operational modes (power-down mode and reset mode) with distinct power supply control paths. The power supply voltage control circuit can selectively connect different circuits to the power supply voltage based on the active mode, allowing reset operations to receive stable power while other circuits remain in low-power state.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

A power supply voltage control circuit acts as an intermediary between the power supply voltage and various circuits. This control circuit receives control signals to determine whether to connect or disconnect the power supply voltage to specific circuits, enabling stable reset operations while maintaining power-down mode benefits for other circuits.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If the semiconductor device maintains power supply voltage during reset operations, then reset stability is improved, but power consumption increases

Engineering Contradiction:

Improvereset operation stabilityVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSLoss of energy

Solution Approach 1:

The power supply system is segmented to provide different power states to different circuits simultaneously. The power supply voltage control circuit enables selective power delivery, maintaining voltage to reset-critical circuits while cutting power to non-essential circuits during reset operations.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Instead of maintaining full power to all circuits during reset, the system applies power selectively only to the extent necessary for stable reset operation. The power supply voltage control circuit limits power delivery to only those circuits that require it for reset functionality.

Inventive Principle:

Principle #16Partial or excessive action

3Loss of energy

If the semiconductor device uses clock enablement signals to manage power-down mode, then power consumption is controlled, but device complexity increases

Engineering Contradiction:

Improvepower consumptionVSAvoidcontrol signal requirements

Core Design Contradiction:

Loss of energyVSDevice complexity

Solution Approach 1:

The patent extracts the power supply voltage control function from the clock enablement mechanism. Instead of using clock signals to gate power delivery, the system uses dedicated power supply voltage control circuits that respond to reset signals and mode signals, simplifying the control architecture.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The power supply voltage control circuit serves multiple functions: it manages power-down mode transitions, supports reset operations, and controls power delivery to various circuits based on operational state. This multi-functional approach eliminates the need for separate clock enablement circuits for each function.

Inventive Principle:

Principle #6Universality (Multi-functionality)

4Loss of energy

If the semiconductor device transitions between power-down and active modes, then power management efficiency is improved, but transition stability may be compromised

Engineering Contradiction:

Improvepower management efficiencyVSAvoidtransition stability

Core Design Contradiction:

Loss of energyVSReliability

Solution Approach 1:

The system performs preliminary actions by asserting a reset signal before transitioning out of power-down mode. This reset signal prepares the circuits for mode transition by initializing their state, ensuring stable operation when power is restored and the device enters active mode.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The power supply voltage control circuit monitors control signals (reset signals and mode signals) to determine the appropriate power supply state. This feedback mechanism ensures that power delivery is adjusted correctly based on the desired operational mode, maintaining transition stability.

Inventive Principle:

Principle #23Feedback

Data Source

PatentUS11435815B2Semiconductor devices providing a power-down mode and methods of controlling the power-down mode using the semiconductor devices

Publication Date: 2022.09.06 SK HYNIX INC

AI summary

A semiconductor device includes a power switch control signal generation circuit. The power switch control signal generation circuit configured to generate a power switch control signal for controlling supply of a power supply voltage based on a reset operation and a power-down mode.