Semiconductor Power-Switch Layout for Low-Resistance Voltage Switching
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Solution Overview
Problem
Existing semiconductor devices face challenges in minimizing wiring resistance from switching circuits to internal circuits, particularly when switching operation voltages for high-speed operations, which affects the efficiency and speed of internal circuit operations.
Innovation Solution
The implementation of power-supply switching circuits with strategically arranged power switches and external power supply lines to minimize wiring resistance, ensuring low-resistance pathways for operation voltages, especially for high-speed operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the switching circuit is placed closer to internal circuits to reduce wiring resistance, then the wiring resistance decreases, but the device layout becomes more complex and harder to manufacture
Solution Approach 1:
The patent utilizes multiple wiring layers (first wiring layer, second wiring layer, third wiring layer) to route power supply lines. By transitioning from a single-plane layout to a multi-layer three-dimensional wiring structure, the patent achieves low wiring resistance while maintaining manufacturable layout complexity through systematic layer assignment and routing rules.
2Reliability
If wider power supply lines are used to reduce wiring resistance, then the wiring resistance decreases, but the area occupied by the circuit increases
Solution Approach 1:
Instead of increasing line width in a single layer, the patent distributes power supply lines across multiple wiring layers (first, second, and third wiring layers). This vertical distribution reduces the area occupied in each individual layer while maintaining low overall wiring resistance through parallel conduction paths.
Solution Approach 2:
The power supply network is segmented into multiple parallel paths across different wiring layers. Each layer carries a portion of the total current, effectively reducing the resistance without requiring any single line to be excessively wide, thus conserving circuit area.
3Reliability
If multiple power supply lines are added to reduce resistance, then the wiring resistance decreases, but the device complexity increases
Solution Approach 1:
The patent adds power supply lines in the vertical dimension by utilizing multiple wiring layers rather than adding horizontal lines in a single plane. This approach reduces resistance through parallel paths while maintaining organized, manufacturable complexity through systematic layer assignment.
Solution Approach 2:
Different wiring layers are assigned specific functions: the first wiring layer handles certain power supply lines, the second wiring layer handles other power supply lines, and the third wiring layer handles signal lines. This local differentiation optimizes each layer's contribution to overall performance while simplifying the design and manufacturing process.
Data Source
AI summary
An apparatus that includes first, second, third and fourth circuit regions arranged in a first direction in numerical order. The first circuit region includes a first global power supply line extending in a second direction vertical to the first direction and a first local power supply line, the first local power supply line being branched from the first global power supply line and extending in the first direction across the second, third and fourth regions. The third circuit region includes a first power switch coupled between the first local power supply line and an internal power supply line extending in the first direction across the first, second, third and fourth regions. Each of the second and fourth regions includes a circuit coupled to the first local power supply line and an additional circuit coupled to the internal power supply line.