Semiconductor Power Delivery Layout for Scaled MOSFET Reliability
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Solution Overview
Problem
The scaling down of metal-oxide-semiconductor field-effect transistors (MOS-FETs) in semiconductor devices leads to deterioration in operational properties, necessitating improvements in electrical and reliability characteristics to maintain high-performance capabilities.
Innovation Solution
The semiconductor device incorporates a substrate with specific patterns, power lines, and penetration vias, along with a power delivery network layer, to enhance electrical connectivity and reliability, including the use of active and tab cells with strategically placed division structures and metal-semiconductor compound layers for improved voltage application and resistance reduction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If MOS-FETs are scaled down to reduce pattern size and design rule, then device integration density increases, but operational properties deteriorate
Solution Approach 1:
The power delivery network is segmented into multiple independent power lines (first power line, second power line, third power line) that are distributed across the substrate. Each power line is independently connected to the power delivery network layer through separate penetration vias, allowing localized power delivery without requiring all transistors to be miniaturized to the same extent.
Solution Approach 2:
Different regions of the substrate are provided with different power line configurations and densities. The power lines are strategically placed to provide localized power delivery to specific transistor regions, allowing critical transistors to receive adequate power even as overall device size decreases.
2Reliability
If power lines are added to improve voltage application, then electrical characteristics improve, but device complexity increases
Solution Approach 1:
Multiple power lines (first, second, and third power lines) are merged into a unified power delivery system that all connect to the same power delivery network layer. This consolidation allows complex power distribution to be achieved through a standardized, repeatable structure rather than through individually complex wiring schemes.
Solution Approach 2:
The power delivery network layer serves multiple functions simultaneously: it provides voltage application to all power lines, acts as a common reference plane, and enables independent power delivery to different transistor regions. This multi-functionality reduces the need for separate structures for each function.
3Reliability
If penetration vias are used to connect power lines to power delivery network, then electrical connectivity improves, but manufacturing complexity increases
Solution Approach 1:
The penetration vias are formed through the substrate before the power lines are deposited. This preliminary formation of via holes through photolithography and etching processes allows subsequent planarization and metal deposition to proceed more easily, reducing the complexity of later manufacturing steps.
Solution Approach 2:
The power delivery network is extended into the vertical dimension by creating a dedicated power delivery network layer below the substrate surface. This three-dimensional arrangement allows penetration vias to provide direct vertical connections, simplifying the routing complexity that would otherwise exist in a purely planar configuration.
Data Source
AI summary
A semiconductor device may include first active patterns adjacent to each other on a substrate, first source/drain patterns respectively on the first active patterns and adjacent to each other, a first division structure and a second division structure crossing the first active patterns and arranged on the substrate such that adjacent ones of the first source/drain patterns are interposed between the first division structure and the second division structure, a first penetration via between adjacent ones of the first source/drain patterns, a first power line on the first penetration via and electrically connected to the first penetration via, a power delivery network layer on a bottom surface of the substrate, and a first lower penetration via between the power delivery network layer and the first penetration via.