Semiconductor Power Line Layout With Vias and Switch Leakage Control
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Solution Overview
Problem
There is a lack of detailed studies on efficiently supplying power supply potential from a subordinate semiconductor chip to a circuit that receives the VDD power supply potential, particularly in configurations with standard cell areas that include buffers or other circuits supplied with the VDD power supply potential.
Innovation Solution
A semiconductor device configuration featuring a first chip with a substrate and multiple wiring layers, including power supply lines and vias connecting them, allows for efficient power supply to circuits by using a switch transistor to control the power supply potential between the VDD and VVDD lines, enabling effective power distribution to buffers and logic circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If power supply potential is supplied from subordinate semiconductor chip to circuit receiving VDD power supply potential, then power consumption is reduced, but power supply efficiency to circuits may be insufficient
Solution Approach 1:
The power supply network is segmented into multiple independent power supply lines (first power supply line for VDD, second power supply line for VVDD, third power supply line for VDD, fourth power supply line for VVDD) that can be independently controlled and routed to different circuit areas. This segmentation allows selective power supply to different circuits, ensuring that circuits receiving VDD power supply potential can be efficiently powered while reducing overall power consumption when those circuits are not active.
Solution Approach 2:
A switch circuit is introduced as an intermediary component connected between the first power supply line and the second power supply line. This switch circuit acts as a mediator that controls the flow of power supply potential between different voltage domains (VDD and VVDD), enabling efficient power distribution to buffers and logic circuits while preventing unnecessary power consumption and leakage current.
2Loss of energy
If switch circuit is connected between VDD power supply line and VVDD power supply line, then leakage current is suppressed, but device complexity increases
Solution Approach 1:
The power supply network is divided into multiple independently controllable power supply lines (first through fourth power supply lines) with dedicated switches for each line. This segmentation allows each switch to be independently controlled based on the specific power supply needs of different circuits, suppressing leakage current in inactive circuits while maintaining simplicity in the overall device architecture through modular switch placement.
Solution Approach 2:
The switch circuits are designed to be dynamically controllable, allowing them to turn on or off based on the operational state of connected circuits. This dynamic control enables the system to adapt power supply connections in real-time, suppressing leakage current when circuits are inactive while maintaining simple device complexity through automated control logic rather than complex hardwired configurations.
3Reliability
If multiple power supply lines are arranged in first area with vias connecting them, then power supply efficiency is improved, but manufacturing complexity increases
Solution Approach 1:
The patent utilizes vertical stacking of wiring layers (first wiring layer on first surface, second wiring layer on second surface) with vias penetrating through the substrate to connect corresponding power supply lines between layers. This three-dimensional arrangement improves power supply efficiency by providing multiple parallel power delivery paths while maintaining ease of manufacture through standardized via formation processes and layered wiring structures that are compatible with existing semiconductor fabrication techniques.
Data Source
AI summary
A semiconductor device has: a first chip having a substrate and a first wiring layer; and a second wiring layer formed on a second surface of the substrate. The second wiring layer has a first power supply line, and a second power supply line. The first chip has a first ground line, a third power supply line, a fourth power supply line, vias formed in the substrate and connecting the first power supply line and the third power supply line, a first area in which the first ground line and the fourth power supply line are arranged, and a first circuit connected between the first ground line and the third power supply line. A switch is connected between the first power supply line and the second power supply line. In a plan view, the third power supply line, the vias, and the first circuit are arranged in the first area.