Semiconductor Pre-Cleaning with Protection Layer for SAC Isolation
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Solution Overview
Problem
As processing nodes for transistors shrink, the self-aligned contact (SAC) process leads to issues such as reduced electrical isolation and increased likelihood of shorting due to protrusions and sidewall spacer thickness reduction, causing current leakage and yield loss in semiconductor devices.
Innovation Solution
A pre-cleaning technique involving a protection layer on capping layers and sidewall spacers to prevent material removal during oxide cleaning, followed by metal silicide formation, which maintains electrical isolation and reduces the likelihood of shorting.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a pre-cleaning process is performed to remove oxides from source/drain regions, then cleaning effectiveness is improved, but material is inadvertently removed from capping layers and sidewall spacers causing protrusions and reduced electrical isolation
Solution Approach 1:
A protection layer is deposited as an intermediary between the pre-cleaning chemistry and the capping layer/sidewall spacer. This protection layer selectively protects the capping layer and sidewall spacer from material removal while allowing the pre-cleaning process to effectively remove oxides from the source/drain regions. The protection layer acts as a mediator that enables the cleaning process to proceed without causing harmful effects to adjacent structures.
Solution Approach 2:
The protection layer is applied in advance of the pre-cleaning process to prevent (anti-action) the unwanted removal of material from the capping layer and sidewall spacer. By establishing this protective barrier before the cleaning process begins, the method preemptively counteracts the harmful effect of material removal, thereby maintaining the critical dimensions and electrical isolation properties of these structures.
2Productivity
If processing nodes are shrunk to increase transistor density, then productivity is improved, but the likelihood of shorting and current leakage increases
Solution Approach 1:
The protection layer is applied in advance to prevent the formation of protrusions that could lead to shorting. By preventing material removal from the capping layer and sidewall spacer before it occurs, the method proactively eliminates the root cause of potential shorting and current leakage, enabling safe scaling to higher transistor densities.
Solution Approach 2:
The protection layer serves as a cushioning barrier that absorbs or mitigates the harmful effects of the pre-cleaning process on the capping layer and sidewall spacer. This beforehand cushioning ensures that even as processing nodes are shrunk and features become more critical, the essential dimensional tolerances and electrical isolation properties are maintained, preventing shorting and enabling higher productivity.
3Manufacturing precision
If sidewall spacer thickness is reduced to enable smaller features, then manufacturing precision is improved, but electrical isolation and reliability deteriorate
Solution Approach 1:
The protection layer acts as an intermediary that enables the sidewall spacer thickness to be reduced to the desired precision level while preventing excessive material removal during pre-cleaning. By selectively protecting the sidewall spacer, the method allows the thickness to be controlled at the target dimension without the harmful side effect of thinning that would compromise electrical isolation and reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances electrical isolation, reduces current leakage, and increases yield by minimizing protrusions and spacer thickness reduction, thereby improving transistor performance.
Implementation Method 1
A protection layer is formed over a gate structure... The protection layer reduces, minimizes, or prevents material removal from the dielectric capping layer during the pre-clean process
Implementation Method 2
perform a pre-clean process to remove native oxides from a top surface of a source/drain region
Implementation Method 3
form a metal silicide layer on the source/drain region... a conductive material is deposited on the source/drain region, and the transistor is subjected to a high-temperature anneal which causes the conductive material to react with silicon of the source/drain region to form the metal silicide layer
Data Source
AI summary
A pre-cleaning technique described herein may be used to remove native oxides and/or other contaminants from a semiconductor device in a manner in which the likelihood of chopping, clipping, and/or sidewall spacer thickness reduction is reduced. As described herein, a protection layer is formed on a capping layer over a gate structure of a transistor. A pre-cleaning operation is then performed to remove native oxides from the top surface of a source/drain region of the transistor. In the pre-cleaning operation, the protection layer is consumed instead of the material of the capping layer. In this way, the use of the protection layer reduces the likelihood of removal of material from the capping layer and/or reduces the amount of material that is removed from the capping layer during the pre-cleaning operation.