Semiconductor Device Layout Shrinking via Pre-Plug Conductive Layer
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Solution Overview
Problem
Semiconductor integrated circuits face inefficiencies in space utilization due to wasted areas in multi-height elements, leading to increased complexity in circuit design and manufacturing processes.
Innovation Solution
A semiconductor device with a pre-plug conductive layer configured as a primary interconnection system, featuring a substrate, gate structure, insulating stacked structure, and a conductive layer with outer extension wings, which allows for a shrunk cell size and improved plug formation process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional multi-height elements are used in integrated circuits, then basic functions can be implemented, but valuable areas are wasted and space utilization efficiency decreases
Solution Approach 1:
The patent transitions from planar 2D layout to 3D vertical stacking by forming insulating stacked structures with conductive layers at different heights. The insulating stacked structure includes multiple insulating layers with a conductive layer embedded between them, creating vertical interconnections that utilize the third dimension (height) to reduce horizontal space occupation. This dimensional change allows circuit elements to be stacked vertically rather than arranged only in the planar direction, thereby improving space utilization efficiency.
Solution Approach 2:
The patent implements nesting by embedding a conductive layer within insulating layers to form an insulating stacked structure. The conductive layer is nested between the first and second insulating layers, creating a compact vertical structure. This nested configuration allows multiple functional layers to occupy the same horizontal footprint while being stacked vertically, effectively reducing the area required for each individual element and improving overall space utilization.
2Reliability
If conventional plug formation processes are used, then interconnections can be formed, but process window is narrow and reliability is compromised
Solution Approach 1:
The patent applies preliminary action by forming the conductive layer within the insulating stacked structure before final plug formation. The conductive layer is embedded between the insulating layers during the stacking process, creating a pre-positioned conductive pathway. This preliminary placement of the conductive layer provides a template and structural support for subsequent plug formation, reducing the difficulty and variability of the plug formation process while improving reliability.
Solution Approach 2:
The conductive layer embedded in the insulating stacked structure serves as an intermediary element that facilitates reliable interconnection. Rather than directly forming plugs between distant elements, the conductive layer acts as an intermediate conductive pathway that simplifies the connection process. This intermediary structure provides mechanical support and electrical continuity, making the overall interconnection process more robust and reliable with a wider process window.
Data Source
AI summary
The present invention relates to a semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a gate structure, an insulating stacked structure and a first conductive layer. The gate structure is disposed on the substrate, and the insulating stacked structure covers the gate structure and the substrate to define a first opening thereinto expose a portion of the gate structure and a portion of the substrate. The first conductive layer covers surfaces of the first opening to directly contact the portion of the substrate and the portion of the gate structure, with the first conductive layer including two outer extension wings on a top surface of the insulating stacked structure.