Semiconductor Predecoder for Superscalar Instruction Prefix Handling
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Solution Overview
Problem
Current data processors with 16-bit fixed-length instruction sets face performance degradation and increased power consumption due to the limited instruction code space, which is not adequately addressed by existing solutions such as implicit fixed register designation and prefix codes that require additional decoding cycles.
Innovation Solution
A data processor is designed with separate prefix code and fixed-length instruction decode units to efficiently decode prefix codes, allowing for function conversion and expansion, and an instruction fetch unit determines whether an instruction is fixed-length or prefixed, enabling efficient superscalar instruction issuance by modifying the operation of fixed-length instructions based on prefix code decoding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If prefix codes are added to expand instruction code space, then instruction versatility is improved, but device complexity and power consumption increase due to additional decoding cycles
Solution Approach 1:
The instruction decode unit is divided into a predecode unit and a main decode unit. The predecode unit extracts prefix codes from instruction codes and outputs them separately, while the main decode unit processes the remaining instruction. This segmentation allows the system to handle prefixed instructions efficiently without requiring a completely separate decoding path, thus reducing device complexity while maintaining instruction versatility.
Solution Approach 2:
The predecode unit performs preliminary processing by extracting prefix codes before the main decoding stage. This preliminary action separates the prefix handling from the main instruction decoding, allowing the main decode unit to focus on core instruction processing. This approach reduces the complexity of the main decode circuit while enabling support for expanded instruction code space through prefix codes.
2Adaptability or versatility
If prefix codes are used to expand instruction functionality, then instruction versatility is improved, but execution time increases due to additional decoding cycles
Solution Approach 1:
The predecode unit performs preliminary extraction of prefix codes in parallel with or before the main decoding process. By identifying and separating prefix codes early in the pipeline, the system can process prefixed instructions more efficiently, reducing the overall execution time compared to sequential processing where prefix decoding would add extra cycles.
Solution Approach 2:
The prefix decoding function is merged into the existing instruction decode pipeline through the predecode unit. Instead of adding separate decoding cycles for prefix handling, the predecode unit integrates prefix extraction with the main instruction decoding flow, allowing both prefix and instruction decoding to occur in a unified, time-efficient manner.
3Productivity
If source forwarding is implemented to compensate for performance degradation from increased transfer instructions, then instruction throughput is improved, but critical path length and power consumption increase
Solution Approach 1:
By using prefix codes to extend instruction functionality, the patent reduces the need for separate transfer instructions. The prefix mechanism allows existing instructions to be enhanced with additional operands or modified behavior, extracting the need for dedicated transfer instructions and reducing their frequency in the instruction stream, thereby reducing the impact on the critical path.
Data Source
AI summary
The present invention realizes an efficient superscalar instruction issue and low power consumption at an instruction set including instructions with prefixes. An instruction fetch unit is adopted which determines whether an instruction code is of a prefix code or an instruction code other than it, and outputs the result of determination and the 16-bit instruction code. Along with it, decoders each of which decodes the instruction code, based on the result of determination, and decoders each of which decodes the prefix code, are disposed separately. Further, a prefix is supplied to each decoder prior to a fixed-length instruction code like 16 bits modified with it. A fixed-length instruction code following the prefix code is supplied to each decoder of the same pipeline as the decoder for the prefix code.