Semiconductor Pressure Sensor With Vertical Cavities
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Solution Overview
Problem
Existing pressure sensors are expensive to fabricate and integrate with sensor circuits due to the need for additional mask levels and significant space on application-specific integrated circuits (ASICs).
Innovation Solution
A semiconductor device with parallel vertical cavities and a pressure-sensitive lamella between them, integrated in a CMOS process, using capacitive, stress-sensitive, or piezo resistor elements to sense pressure, minimizing area and cost, and fabricated using a single chip with logic devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a stand-alone pressure sensor is coupled to or bonded to a sensor circuit, then pressure sensing function is achieved, but fabrication cost and integration cost are high
Solution Approach 1:
The patent merges the pressure sensor structure with the semiconductor substrate containing the sensor circuit into a single integrated device. The first cavity for pressure sensing and the second cavity for reference pressure are both formed within the same semiconductor substrate, eliminating the need for separate stand-alone pressure sensor components and their associated bonding and integration processes.
Solution Approach 2:
The semiconductor substrate serves multiple functions: it provides the structural platform for the pressure sensing cavities, contains the sensor circuit for signal processing, and integrates both the active pressure sensing element and the reference pressure cavity. This multi-functional integration reduces both component count and manufacturing complexity.
2Adaptability or versatility
If a pressure sensor is integrated with a sensor circuit during a back-end-of-line process, then integration is achieved, but additional mask levels are required and space on ASIC is significant
Solution Approach 1:
The patent transitions from planar integration to three-dimensional vertical integration by forming cavities that extend through the semiconductor substrate. The first cavity and second cavity are positioned at different vertical levels within the substrate, allowing pressure sensing functionality to be added without consuming additional lateral space on the ASIC surface.
Solution Approach 2:
The pressure sensing cavities are nested within the semiconductor substrate structure, with the first cavity and second cavity embedded in the substrate volume. This nesting approach allows the pressure sensor functionality to be contained within the existing substrate footprint, minimizing additional space requirements on the ASIC.
3Reliability
If multiple cavities and sensor elements are integrated in a single chip, then reliability is increased through arrays, but fabrication process complexity increases
Solution Approach 1:
The patent segments the pressure sensing function into multiple independent cavities (first cavity and second cavity) and multiple sensor elements within the same semiconductor substrate. This segmentation provides redundancy and improved reliability, as individual elements can fail without compromising the entire sensor array's functionality.
Solution Approach 2:
The patent utilizes standard CMOS fabrication process parameters and materials to create the cavities and sensor elements, maintaining compatibility with existing manufacturing processes. By using established process parameters rather than introducing new complex processes, the fabrication complexity is minimized while still achieving multiple integrated cavities and sensor elements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides low-cost, highly sensitive, and reliable pressure sensors that consume minimal area, with increased reliability through arrays of cavities and sensor elements, and can be integrated into ASICs, reducing fabrication costs and space requirements.
Implementation Method 1
using capacitive, stress-sensitive, or piezo resistor elements to sense pressure
Implementation Method 2
using capacitive, stress-sensitive, or piezo resistor elements to sense pressure
Implementation Method 3
using capacitive, stress-sensitive, or piezo resistor elements to sense pressure
Data Source
AI summary
A semiconductor device includes a first cavity within a semiconductor substrate and a second cavity within the semiconductor substrate. The second cavity is open to an atmosphere and defines a first lamella between the first cavity and the second cavity. The semiconductor device includes a first sense element configured for sensing a pressure on the first lamella.