Semiconductor Processing Unit Error Recovery via Data Preservation

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Solution Overview

Problem

Existing semiconductor devices fail to effectively manage data integrity when an abnormal processing unit is reset, as there is a risk of data being overwritten or lost, and cannot detect adverse effects on normal processing units during the transition.

Innovation Solution

A semiconductor device with multiple processing units, a processing control unit, and a storage unit that writes information about each processing unit's operations, allowing the control unit to stop the faulty unit and determine if a secondary unit can maintain execution based on stored information, ensuring continuous processing and preventing malfunctions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If an abnormal processing unit is reset after detecting an error, then the processing unit can be restored to normal operation, but data may be overwritten or lost during the period from error detection to reset

Engineering Contradiction:
Improveprocessing unit restorationVSAvoiddata integrity
Core Design Contradiction:
ReliabilityVSLoss of information

Solution Approach 1:

The patent applies preliminary action by writing processing information to storage unit 104 before the abnormal processing unit is reset. The writing unit 103 records data about the abnormal processing unit's operations in advance, so that even if data is lost during reset, the processing information is already preserved in the storage unit, preventing information loss while maintaining the ability to restore the processing unit.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If a normal processing unit continues processing after an abnormal processing unit becomes abnormal, then processing continuity is maintained, but the normal processing unit may be adversely affected by the abnormal processing unit's operations

Engineering Contradiction:
Improveprocessing continuityVSAvoidprocessing safety
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent implements feedback by having the processing control unit 102 monitor processing information stored in the storage unit 104. The control unit checks whether the abnormal processing unit's operations have adversely affected other processing units based on the recorded processing information, and can detect and prevent potential harm while maintaining processing continuity through normal units.

Inventive Principle:
Principle #23Feedback

3Reliability

If multiple processing units are placed in a single semiconductor device to enable task takeover, then system reliability is improved, but the complexity of managing data integrity and error detection increases

Engineering Contradiction:
Improvetask takeover capabilityVSAvoiderror management complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent introduces an intermediary approach by using a storage unit 104 that acts as a mediator between multiple processing units 101. The writing unit 103 and processing control unit 102 manage the storage unit to record and monitor processing information, simplifying the coordination and error management between processing units while maintaining the ability to detect adverse effects and ensure data integrity.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS10579487B2Semiconductor device and control method thereof including a plurality of processing units
Publication Date: 2020.03.03 RENESAS ELECTRONICS CORP
  • US10579487B2 patent drawing
  • US10579487B2 patent drawing
  • US10579487B2 patent drawing

AI summary

A semiconductor device (1) includes a first processing unit (10-1), a second processing unit (10-2), a writing unit (12), a storage unit (14), and a processing control unit (20). The writing unit (12) writes first information related to processing of each of the first processing unit (10-1) and the second processing unit (10-2) into the storage unit (14). The processing control unit (20) controls the operations of the first processing unit (10-1) and the second processing unit (10-2). The processing control unit (20) performs control to stop the first processing unit (10-1) when an error occurs in the first processing unit (10-1). When it is determined that the second processing unit (10-2) where an error has not occurred is able to maintain execution of the first processing by using first information stored in the storage unit (14), the second processing unit (10-2) maintains execution of the first processing.