Semiconductor Device Program Disabling Circuit
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Solution Overview
Problem
Existing non-volatile memory technologies face challenges in disabling programming in multiple memory regions simultaneously while maintaining a smaller circuit area and ensuring high security, with issues related to varying programming times and the need for multiple latch circuits, as well as the coexistence of STB and collective erasing functions.
Innovation Solution
A semiconductor device with a program disabling information selection circuit that outputs collective program disabling information to enable or disable programming across multiple memory regions, along with a disabling information control circuit that prohibits changes from a program disabling state to a program enabling state, and separate erasing units for different memory units to prevent simultaneous erasing and enhance security.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple latch circuits are provided for each write protect memory circuit to set program disabling information simultaneously, then the security level is improved, but the circuit area increases and programming time varies
Solution Approach 1:
Multiple latch circuits are merged into a single latch circuit that processes program disabling information for multiple memory regions simultaneously. This consolidation reduces the overall circuit area while maintaining the security function of simultaneous information setting across all memory regions.
Solution Approach 2:
A single latch circuit is designed to handle program disabling information for multiple memory regions, making it a multi-functional component. This universal latch circuit replaces multiple dedicated latch circuits, reducing circuit area while maintaining simultaneous security control across all regions.
2Reliability
If multiple latch circuits are provided for each write protect memory circuit to set program disabling information simultaneously, then the security level is improved, but the programming time increases due to dispersion
Solution Approach 1:
Multiple latch circuits are merged into a single latch circuit that processes program disabling information for multiple memory regions simultaneously. This consolidation reduces the overall circuit area while maintaining the security function of simultaneous information setting across all memory regions.
3Reliability
If ROM information is set in response to user request or by authorized users only, then security against falsification is improved, but the device complexity increases
Solution Approach 1:
The system provides self-service security control where the non-volatile memory automatically manages ROM information setting based on built-in authorization mechanisms. The control circuit identifies authorized users and automatically sets ROM information without requiring external intervention, simplifying the overall control mechanism while maintaining high security.
4Productivity
If programming is disabled collectively in multiple memory regions, then the operation efficiency is improved, but the control complexity increases
Solution Approach 1:
A single program disabling information selection circuit is designed to control multiple memory regions simultaneously. This multi-functional circuit receives program disabling information and distributes it to multiple memory regions, enabling collective programming disablement while keeping the control circuit relatively simple.
Data Source
AI summary
A semiconductor device includes: memory regions that include non-volatile memory cells; disabling information memory units that correspond to the memory regions, each of the disabling information memory units storing first program disabling information indicating whether programming is to be disabled or enabled in each corresponding memory region; a program disabling information selection circuit that outputs second program disabling information for disabling programming in a corresponding memory region, regardless of the first program disabling information, when programming is disabled collectively in the memory regions in accordance with collective program disabling information indicating whether programming is to be disabled collectively in the memory regions, the program disabling information selection circuit outputting the first program disabling information as the second program disabling information when programming is not collectively disabled; and a program control circuit that disables or enables programming in the corresponding memory region in accordance with the second program disabling information.