Semiconductor Program Operation Control via Dynamic Bit Line Voltage
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Solution Overview
Problem
The characteristic degradation of program operation in semiconductor memory devices, particularly in flash memory, due to the imbalance in programming and verification processes, leading to inefficiencies and reduced performance over time.
Innovation Solution
A semiconductor apparatus with a control circuit that performs a program operation on target cells within a memory cell array, utilizing multiple loops with varying bit line voltages and pass voltages, including a first program control operation, a second program control operation, and a third program control operation, to optimize the programming process and mitigate characteristic degradation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional program operation is performed with fixed bit line voltage levels across all loops, then the program operation can be completed with simple control logic, but the program operation characteristics degrade due to imbalance in programming and verification processes
Solution Approach 1:
The patent applies dynamics by making the bit line voltage level variable across different loops rather than fixed. The control circuit dynamically adjusts the bit line voltage to a higher level in loops where pass voltage at a second level is applied, and maintains a predetermined level in loops where pass voltage at a first level is applied. This dynamic adjustment resolves the contradiction by adapting the voltage levels to the specific programming stage, improving program operation characteristics while managing control complexity through systematic voltage scheduling.
2Reliability
If more loops are added to improve verification accuracy, then the program operation reliability improves, but the program operation time increases
Solution Approach 1:
The patent implements periodic action through its multi-loop structure where verification operations are performed periodically at different voltage levels. The control circuit systematically cycles through multiple loops, applying different pass voltage levels and corresponding bit line voltage levels in each loop. This periodic verification approach improves verification accuracy by checking program status at multiple stages while managing time loss through efficient voltage level transitions and targeted verification at critical loops.
3Productivity
If bit line voltage is increased in all loops to improve programming speed, then the program operation speed improves, but the energy consumption and device stress increase
Solution Approach 1:
The patent applies local quality by applying different bit line voltage levels to different loops based on their specific programming requirements. Instead of uniformly increasing voltage across all loops, the control circuit selectively applies a higher bit line voltage level only in loops where pass voltage at a second level is applied, while maintaining the predetermined voltage level in other loops. This localized voltage enhancement improves programming speed where needed while minimizing overall energy consumption and device stress.
Data Source
AI summary
A semiconductor apparatus includes a memory cell array and a control circuit. The control circuit is configured to perform a program operation on target cells within the memory cell array, the program operation including a plurality of loops. The control circuit may be configured to apply a bit line voltage having a predetermined level to bit lines in loops in which a pass voltage having a first level is applied among the plurality of loops, and configured to apply the bit line voltage having a higher level than the predetermined level to the bit lines in loops in which the pass voltage having a second level higher than the first level is applied among the plurality of loops.