Semiconductor Device Programming Speed Power Consumption
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Solution Overview
Problem
Current semiconductor devices face challenges in reducing power consumption while maintaining high programming speed for nonvolatile memory transistors, which is crucial for efficient data storage in systems with varying capacities.
Innovation Solution
The semiconductor device incorporates a gate insulator layer, sidewall insulator layers, source and drain regions, and a third semiconductor region with specific impurity concentrations to store information by injecting charge into the sidewall insulator layer, with voltage configurations that optimize programming speed and reduce power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the programming speed of memory transistors is improved by conventional methods, then programming speed increases, but power consumption increases
Solution Approach 1:
The patent applies local quality by creating semiconductor regions with different impurity concentrations in specific locations. The first and second semiconductor regions have lower impurity concentrations than the source and drain regions, respectively, while the third semiconductor region has higher impurity concentration than the channel region. This localized variation in impurity concentration optimizes the electric field distribution specifically in the programming region, enabling reduced programming current while maintaining high programming speed.
Solution Approach 2:
The patent changes the impurity concentration parameter of the semiconductor substrate to resolve the contradiction. By introducing semiconductor regions with specifically controlled impurity concentrations (lower than source/drain regions and higher than the channel region), the patent modifies the electrical characteristics of the programming path, enabling reduced programming current while maintaining high programming speed.
2Speed
If the impurity concentration of the semiconductor substrate is increased to improve programming speed, then programming speed improves, but programming current increases leading to higher power consumption
Solution Approach 1:
Instead of uniformly increasing impurity concentration throughout the semiconductor substrate, the patent applies local quality by creating specific semiconductor regions with varied impurity concentrations. The first and second semiconductor regions have lower impurity concentrations than the source and drain regions, while the third semiconductor region has higher impurity concentration than the channel region. This localized approach improves programming speed without requiring high overall impurity concentration, thereby reducing programming current and power consumption.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration significantly decreases programming current and power consumption while improving programming speed, enabling efficient data storage within tolerable time frames even in systems with large capacities.
Implementation Method 1
a first voltage higher than a ground potential is applied to the gate electrode
Implementation Method 2
a second voltage higher than the ground potential is applied to the drain region
Implementation Method 3
a third voltage higher than the ground potential and lower than the first voltage and the second voltage is applied to the source region
Data Source
AI summary
A semiconductor device includes a gate insulator layer above a semiconductor substrate, a gate electrode above the gate insulating layer, a sidewall insulator layer on sidewalls of the gate electrode and above the substrate, source and drain regions within the substrate on both sides of the gate electrode, a first region within the substrate below a part of the sidewall insulator layer closer to the source region and having an impurity concentration lower than the source region, a second region provided within the substrate below a part of the sidewall insulator layer closer to the drain region and having an impurity concentration lower than the drain region, a channel region provided within the substrate between the first and second regions, and a third region within the substrate below the channel region and including impurities of a different type and having an impurity concentration higher than the channel region.