Semiconductor Chip Projections for Void-Free Flip-Chip Bonding
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Solution Overview
Problem
Conventional semiconductor devices experience unstable electrical connections due to air voids formed during bonding resin injection, which can deform and destabilize the chip-substrate attachment, especially at the boundary surface where adhesive strength is lowest, leading to increased manufacturing costs and complexity.
Innovation Solution
The semiconductor device features projections between pads arranged in staggered annular concentric layers on the semiconductor chip, with each projection having a trapezoidal cross-section, slits, and a recessed top surface, allowing the bonding resin to flow smoothly and preventing air voids, while maintaining the stability of electrical connections without additional manufacturing steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If bonding resin is injected using capillary action from outside to inside, then the gap is filled with bonding resin, but air voids are formed due to entrainment
Solution Approach 1:
The patent inverts the conventional capillary action direction by providing projections that extend from the substrate toward the semiconductor chip, allowing bonding resin to flow from the inside (center) outward. This reverse flow pattern prevents air entrapment and void formation while maintaining complete gap filling, thereby resolving the contradiction between manufacturing precision and reliability.
Solution Approach 2:
The projections serve as intermediary structures between the substrate and semiconductor chip, creating controlled flow paths for the bonding resin. These projections mediate the resin flow process, guiding it to move smoothly from the center outward and preventing air void formation, thus improving both gap filling completeness and electrical connection stability.
2Reliability
If projections are added between bumps to suppress void formation, then void formation is reduced, but manufacturing steps and cost increase
Solution Approach 1:
The patent merges the projection formation process with the existing bump formation process. The projections are formed using the same reflow soldering step that creates the bumps, eliminating the need for separate projection formation steps. This integration reduces manufacturing complexity while maintaining void formation suppression benefits.
Solution Approach 2:
The projections serve multiple functions: they act as flow guides for bonding resin, provide mechanical support, and prevent void formation. By making the projections multi-functional, the patent avoids adding dedicated structures for each function, thereby reducing overall device complexity while achieving reliable void suppression.
3Reliability
If adhesive strength is increased at boundary surface, then void prevention improves, but manufacturing complexity increases
Solution Approach 1:
The patent applies local quality by providing projections at specific locations (between bumps in the outer peripheral region) rather than uniformly across the entire bonding interface. This localized approach enhances adhesion and prevents void formation at the most critical boundary surface areas without requiring complex modifications throughout the entire structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design stabilizes the electrical connection between the semiconductor chip and substrate by ensuring complete resin flow and adhesion, preventing void formation and enhancing the chip's securement to the substrate, thus maintaining reliable electrical connections without increasing manufacturing complexity or costs.
Implementation Method 1
the bonding resin is injected into a gap between the substrate and the semiconductor chip by using a capillary action that facilitates the bonding resin to spread through the gap from the outside to the inside of the semiconductor chip
Data Source
AI summary
When manufacturing a semiconductor device by mounting a semiconductor chip 2 on a substrate 1 with a flip-chip method, projections 9 are formed between pads 4 arranged in multiple annular concentric layers on the semiconductor chip 2 other than pads 4 arranged along the innermost periphery thereof. On the substrate 1, bonding resin 3 is dispensed onto an area inside the innermost periphery along which the pads 4 are arranged. By heating and applying pressure, the bonding resin 3 is spread over the entire gap between the substrate 1 and the semiconductor chip 2 so as to secure the substrate 1 to the semiconductor chip 2 by the bonding resin 3, thereby preventing a void from being formed in an area outside the innermost periphery along which the pads 4 are arranged and thus stabilizing an electrical connection state between the semiconductor chip 2 and the substrate 1.