Semiconductor Protection Device Reducing Parasitic Capacitance
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Solution Overview
Problem
Semiconductor devices, especially RF devices, are sensitive to the parasitic capacitance caused by protection diodes during testing, leading to measurement deviations due to large parasitic capacitance.
Innovation Solution
A protection device is designed with a doped well and semiconductor terminals of different impurity types, connected to a voltage level and ground, featuring insulating layers and strategically sized and shaped junction capacitors to reduce parasitic capacitance and provide bi-directional protection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a protection diode is connected to pads to protect semiconductor devices from high voltage or large current, then protection capability is improved, but parasitic capacitance increases causing measurement deviation
Solution Approach 1:
The protection device is segmented into multiple P-N junctions (first P-N junction between first doped well and first semiconductor terminal, second P-N junction between second doped well and second semiconductor terminal) instead of using a single protection diode. This segmentation distributes the parasitic capacitance across multiple junctions, reducing the total effective parasitic capacitance while maintaining protection capability through bi-directional voltage clamping
Solution Approach 2:
The first and second semiconductor terminals are designed with different areas (first terminal area ≠ second terminal area), creating asymmetric P-N junctions with different capacitance values. This asymmetric design allows optimization of the protection characteristics while managing parasitic capacitance effects, particularly for RF devices sensitive to capacitance
2Object-affected harmful factors
If protection diode is used at pads, then electrostatic protection is provided, but parasitic capacitance causes measurement shift in RF devices
Solution Approach 1:
The invention introduces doped wells (first doped well with first conductivity type, second doped well with second conductivity type) as intermediary structures between the semiconductor terminals and the substrate. These intermediary wells create additional P-N junctions that act as capacitance buffers, reducing the direct parasitic capacitance effect on RF signal measurements while maintaining electrostatic protection function
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces parasitic capacitance, minimizing measurement deviations and providing robust protection against unexpected voltages, making it suitable for sensitive semiconductor devices like RF transistors.
Implementation Method 1
The protection diode usually has a parasitic capacitor exiting at the P-N junction. This parasitic capacitor usually has a large parasitic capacitance.
Implementation Method 2
a first junction capacitor formed between the first semiconductor terminal and the doped well, and a second junction capacitor formed between the second semiconductor terminal and the doped well
Data Source
AI summary
A method for fabricating a protection device includes forming a doped well with a first-type impurity in a substrate. A first semiconductor terminal with a second-type impurity is formed on the doped well. A second semiconductor terminal with a second-type impurity is formed on the doped well separating from the first semiconductor terminal. The first semiconductor terminal is connected to a voltage level and a second semiconductor terminal is connected to a ground voltage.