Insulated Gate Semiconductor Device Parallel Protection Diode Segmentation
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Solution Overview
Problem
Conventional insulated gate semiconductor devices face challenges in achieving high electrostatic discharge (ESD) tolerance while maintaining a small chip size and low on-state resistance, as increasing the area of protection diodes to enhance ESD tolerance leads to increased chip size and higher on-state resistance.
Innovation Solution
The solution involves dividing a conventional single protection diode into multiple protection diodes connected in parallel, with each diode having multiple concentric pn junctions, allowing for a reduced total junction area average that maintains desired ESD tolerance while minimizing the occupation area on the chip.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the total area of pn junctions constituting the protection diode is increased to enhance ESD tolerance, then the ESD tolerance is improved, but the area occupied by the protection diode on the chip is increased
Solution Approach 1:
The invention divides a single protection diode structure into multiple protection diodes (first protection diode and second protection diode) connected in parallel. Each protection diode contains multiple pn junctions, but the total junction area average of the group is reduced compared to a single large protection diode. This segmentation allows achieving the same ESD tolerance through parallel configuration rather than increasing the area of a single diode.
2Reliability
If the junction area of the protection diode is increased to enhance ESD tolerance, then the ESD tolerance is improved, but the operating region of the chip is reduced
Solution Approach 1:
By segmenting the protection diode into multiple smaller diodes connected in parallel, the total occupation area is reduced while maintaining ESD tolerance. This frees up chip area for the operating region, allowing more transistor cells to be disposed on the chip without compromising ESD protection capability.
3Reliability
If the junction area of the protection diode is increased to enhance ESD tolerance, then the ESD tolerance is improved, but the chip size is increased
Solution Approach 1:
The parallel configuration of multiple protection diodes with reduced individual junction areas achieves the same ESD tolerance as a single large protection diode. This segmentation strategy reduces the total area required for the protection diode group, thereby reducing the overall chip size while maintaining the same ESD protection level.
4Productivity
If the protection diode occupation area is reduced to increase operating region, then the on-state resistance is reduced, but the ESD tolerance may be compromised
Solution Approach 1:
The invention resolves this contradiction by using multiple protection diodes in parallel, each with multiple pn junctions. The total junction area average is controlled to be reduced compared to conventional single protection diodes, while the parallel configuration maintains the ESD tolerance. This allows reducing the protection diode occupation area, increasing the operating region, and lowering the on-state resistance without compromising ESD protection.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces the occupation area of the protection diode group on the chip, allowing for an increased operating region and lower on-state resistance, while ensuring equivalent ESD tolerance and other characteristics to conventional protection diodes.
Implementation Method 1
protect a thin gate insulating film (oxide film) against electrostatic discharge (hereinafter, ESD)
Implementation Method 2
each of the first and second protection diodes has a plurality of pn junctions formed between a p type semiconductor region and an n type semiconductor region
Data Source
AI summary
A protection diode group includes multiple protection diodes connected to each other in parallel. A total junction area average of the protection diode group is set to a value large enough to guarantee a desired electrostatic discharge tolerance. By setting the total junction area average to be equal to a junction area average of a conventional structure, the occupation area of the protection diode group on the chip is reduced while the ESD tolerance is made equal to a conventional ESD tolerance.


