Semiconductor Protection IC with Dynamic Delay Reduction
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Solution Overview
Problem
Conventional protection ICs for rechargeable battery packs face challenges in efficiently managing excessive discharge currents, requiring multiple delay times and increasing IC chip size and cost due to the need for sophisticated control mechanisms.
Innovation Solution
A semiconductor device with multiple excessive discharge current detection circuits and a delay reducing circuit that adjusts delay times based on voltage levels at the electric current detection terminal, allowing for different levels of discharge current protection without expanding the IC chip area, using a combination of CMOS inverters and NMOS transistors to generate a delay time reducing signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple delay times are arranged for different excessive discharge current levels, then protection precision is improved, but IC chip area and cost increase
Solution Approach 1:
The patent merges multiple delay time functions into a single delay circuit by using a delay reducing circuit that dynamically adjusts the delay time based on voltage level detection. Instead of implementing separate delay circuits for each excessive discharge current level, the invention combines them into one circuit that adapts its delay characteristic according to the detected voltage level, thereby reducing IC chip area while maintaining protection precision.
Solution Approach 2:
The patent applies dynamics by making the delay time adjustable rather than fixed. The delay reducing circuit changes the delay time dynamically based on the voltage level detected at the electric current detection terminal. This allows a single delay circuit to provide multiple delay characteristics (different delay times for different excessive discharge current levels) without requiring multiple separate circuits, thus resolving the contradiction between protection precision and IC chip area.
2Ease of manufacture
If external capacitors are used to determine delay time, then delay time adjustment is simple, but device size and cost increase
Solution Approach 1:
The patent extracts the delay time determination function from external capacitors and integrates it into the IC chip itself. The delay reducing circuit uses voltage level detection and internal timing mechanisms to generate appropriate delay times without requiring external capacitor components. This eliminates the need for external capacitors while maintaining the ability to adjust delay times for different protection levels, thereby reducing device size while keeping manufacturing simple.
Solution Approach 2:
The patent replaces the mechanical/electrical system of external capacitors with an integrated electronic solution. Instead of using physical external capacitors to set delay times, the invention uses voltage-level-dependent electronic control within the IC to achieve the same delay time adjustment function. This substitution reduces device size while maintaining ease of manufacture through standard IC fabrication processes.
3Productivity
If delay time is shortened for inspection, then productivity is improved, but protection reliability may be compromised
Solution Approach 1:
The patent applies dynamics by enabling flexible adjustment of delay times based on operational context. During inspection, the delay reducing circuit can be configured to provide shorter delay times to speed up testing and improve productivity. During normal operation, appropriate delay times are maintained to ensure protection reliability. This dynamic adjustability allows the system to optimize for different operational requirements without compromising either productivity or reliability.
Solution Approach 2:
The patent changes the delay time parameter dynamically based on the operational mode. By using voltage level detection and control circuits, the system can adjust the delay time parameter to different values depending on whether it is in inspection mode or normal protection mode. This parameter change capability allows short delay times during inspection for high productivity while maintaining appropriate delay times during normal operation for reliable protection.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables precise management of excessive discharge currents by adjusting delay times, reducing the IC chip area and cost, while preventing error operations from noise or jitter through hysteresis characteristics in the delay reducing circuit.
Implementation Method 1
preventing error operations from noise or jitter through hysteresis characteristics in the delay reducing circuit
Data Source
AI summary
A semiconductor device for protecting a rechargeable cell at least from excessive discharge current due to over discharge of the rechargeable cell, includes (a) a first excessive discharge current detection circuit configured to detect first excess of a voltage at an electric current detection terminal exceeding a first voltage level (Vs3), (b) a second excessive discharge current detection circuit configured to detect second excess of the absolute voltage at the electric current detection terminal exceeding a second voltage level (Vs4) higher than the first voltage level, (c) a delay circuit configured to cause each of the first and second excessive discharge current detection circuits to delay output by a predetermined delay time, and (d) a delay reducing circuit configured to produce a delay time reducing signal for reducing the delay time at a predetermined ratio.