Semiconductor Package Protection Layer Prevents Barrier Loss

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Solution Overview

Problem

Semiconductor packages face challenges in achieving higher performance, larger capacity, miniaturization, and lightness while maintaining reliability, particularly due to issues with the peeling off of conductive patterns caused by loss of barrier layers during manufacturing.

Innovation Solution

The semiconductor package design includes a protection layer covering the bottom surface of the barrier layer, a conductive pattern extending through the protection layer, and a barrier layer conformally covering the conductive pattern, along with multiple insulating layers and redistribution patterns, which helps in preventing the peeling off of the conductive pattern and enhancing the overall reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a conventional manufacturing process is used without a protection layer, then the manufacturing process is simpler and faster, but the barrier layer is lost during manufacturing causing conductive pattern peeling and reduced reliability

Engineering Contradiction:
ImprovereliabilityVSAvoidstructure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

A protection layer is formed over the barrier layer and conductive pattern before subsequent manufacturing steps. This protection layer prevents the barrier layer from being lost during manufacturing processes, thereby preventing conductive pattern peeling and enhancing reliability. The protective structure is established in advance to safeguard against future damage.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The protection layer serves as a cushioning structure that protects the vulnerable barrier layer and conductive pattern from damage during manufacturing. By providing this protective barrier beforehand, the structure compensates for potential losses that would otherwise occur during subsequent processing steps.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

2Loss of substance

If the barrier layer is kept thin to reduce material usage, then material cost is reduced, but the barrier layer becomes more susceptible to loss during manufacturing

Engineering Contradiction:
ImprovematerialVSAvoidreliability
Core Design Contradiction:
Loss of substanceVSReliability

Solution Approach 1:

The protection layer is formed over the thin barrier layer before manufacturing steps that could cause material loss. This allows the use of thinner barrier layers for material efficiency while the protection layer prevents their loss during subsequent processing, maintaining reliability despite reduced material thickness.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If multiple manufacturing steps are added to prevent barrier layer loss, then reliability is improved, but manufacturing time and cost increase

Engineering Contradiction:
ImprovereliabilityVSAvoidmanufacturing time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The protection layer is formed as an integrated part of the manufacturing sequence, combining the protective function with the existing manufacturing flow. Rather than adding separate protective measures, the protection layer is incorporated into the standard fabrication process, minimizing additional time and cost while ensuring reliability.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS20230025903A1Semiconductor package including redistribution structure and method for manufacturing the same
Publication Date: 2023.01.26 SAMSUNG ELECTRONICS CO LTD
  • US20230025903A1 patent drawing
  • US20230025903A1 patent drawing
  • US20230025903A1 patent drawing

AI summary

A semiconductor package according to the disclosure includes a terminal, a conductive pattern connected to the terminal, a barrier layer covering a top surface and a first side wall of the conductive pattern, an insulating layer surrounding the barrier layer, a protection layer covering a bottom surface of the insulating layer and a bottom surface of the barrier layer, a redistribution pattern connected to the barrier layer, a semiconductor chip electrically connected to the redistribution pattern, and a molding layer surrounding the semiconductor chip. A top surface of the protection layer includes a first portion contacting the conductive pattern, and a second portion contacting the barrier layer.