Semiconductor Package Protection Layer Fabrication

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing semiconductor packages lack effective protection against external damage, which compromises their reliability and requires complex molding processes, making them costly and inefficient.

Innovation Solution

A method for fabricating a semiconductor package that involves forming a protection layer over semiconductor chips on a support substrate, followed by a molding layer, and then etching to expose the protection layer, which prevents damage during processing and simplifies the structure by eliminating the need for a printed circuit board.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a molding process is used to protect semiconductor chips, then reliability is improved, but device complexity and manufacturing cost increase

Engineering Contradiction:
Improveprotection from external damageVSAvoidmolding process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent extracts the essential protective function from the complex molding process. Instead of using traditional molding that requires molds, clamps, and multi-step operations, the invention applies a simple protection layer directly formed on the chip surface, eliminating the need for complex molding equipment and processes while maintaining the protective function.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The protection layer is applied locally only where needed on the semiconductor chip surface, rather than enclosing the entire chip in a bulky mold. This localized approach provides protection against external damage while avoiding the complexity and size increase associated with full encapsulation molding processes.

Inventive Principle:
Principle #3Local quality

2Reliability

If a molding process is used to protect semiconductor chips, then reliability is improved, but manufacturing cost increases

Engineering Contradiction:
Improveprotection from external damageVSAvoidmanufacturing cost
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The invention extracts the core protective function from the expensive molding process. By using a simple protection layer formation method that avoids costly molds, clamps, and complex molding equipment, the solution maintains reliability while significantly reducing manufacturing costs.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The protection layer uses simple, inexpensive materials and a straightforward formation process that can be easily applied and removed or replaced if needed, avoiding the high capital investment and ongoing costs associated with traditional molding processes.

Inventive Principle:
Principle #27Cheap short-living objects (Disposable)

3Ease of operation

If a printed circuit board is used in the package structure, then electrical connections are achieved, but device complexity and size increase

Engineering Contradiction:
Improveelectrical connection capabilityVSAvoidpackage structure complexity
Core Design Contradiction:
Ease of operationVSDevice complexity

Solution Approach 1:

The patent merges the electrical connection function directly into the chip structure itself, eliminating the need for a separate printed circuit board. The chip is designed with integrated connection elements that provide electrical connectivity without requiring an additional PCB layer, thereby reducing overall package complexity.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The semiconductor chip is designed to perform multiple functions: it provides both the active electronic function and the electrical connection function through integrated connection elements. This multi-functionality eliminates the need for separate dedicated connection components like printed circuit boards, simplifying the overall package structure.

Inventive Principle:
Principle #6Universality (Multi-functionality)

4Ease of operation

If a printed circuit board is used in the package structure, then electrical connections are achieved, but package size increases

Engineering Contradiction:
Improveelectrical connection capabilityVSAvoidpackage size
Core Design Contradiction:
Ease of operationVSVolume of moving object

Solution Approach 1:

The invention merges the electrical connection function directly into the chip structure, eliminating the need for a separate printed circuit board. This integration removes the additional space required for PCB traces, vias, and mounting structures, thereby reducing the overall package size.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The connection elements are nested directly within or on the chip structure itself, rather than requiring external PCB infrastructure. This nesting approach allows electrical connections to be made in a compact configuration, minimizing the volume required for the package.

Inventive Principle:
Principle #7Nested doll (Nesting)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances the reliability of semiconductor packages by protecting them from external damage and simplifies the manufacturing process, reducing costs and complexity by eliminating the need for a molding process and printed circuit board.

Implementation Method 1

etching the molding layer formed on the protection layer to expose the protection layer

Methodology Applied
Scientific EffectEtching:

Data Source

PatentUS9589842B2Semiconductor package and method of fabricating the same
Publication Date: 2017.03.07 SAMSUNG ELECTRONICS CO LTD
  • US9589842B2 patent drawing
  • US9589842B2 patent drawing
  • US9589842B2 patent drawing

AI summary

A method of fabricating a semiconductor package is disclosed. The method includes disposing semiconductor chips on a support substrate, forming a protection layer covering top surfaces of the semiconductor chips, forming a molding layer covering the support substrate and the protection layer, and etching the molding layer to expose the protection layer.